The LMV393-N and LMV339-N are low-voltage (2.7 to 5 V) versions of the dual and quad comparators, LM393/339, which are specified at 5 to 30 V. The LMV331-N is the single version, which is available in space-saving, 5-pin SC70 and 5-pin SOT23 packages. The 5-pin SC70 is approximately half the size of the 5-pin SOT23.
The LMV393-N is available in 8-pin SOIC and VSSOP packages. The LMV339-N is available in 14-pin SOIC and TSSOP packages.
The LMV331-N/393-N/339-N is the most cost-effective solution where space, low voltage, low power, and price are the primary specification in circuit design for portable consumer products. They offer specifications that meet or exceed the familiar LM393/339 at a fraction of the supply current.
The chips are built with TI's advanced Submicron Silicon-Gate BiCMOS process. The LMV331-N/393-N/339-N have bipolar input and output stages for improved noise performance.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMV331-N | SC70 (5) | 2.00 mm × 1.25 mm |
SOT-23 (5) | 2.90 mm × 1.6 mm | |
LMV339-N | SOIC (14) | 8.65 mm × 3.91 mm |
TSSOP (14) | 5.00 mm × 4.40 mm | |
LMV393-N | SOIC (8) | 4.90 mm × 3.91 mm |
VSSOP (8) | 3.00 mm × 3.00 mm |
Changes from G Revision (Feburary 2013) to H Revision
PIN | TYPE | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | LMV331-N DVB,DCK |
LMV393-N D,DGK |
LMV339-N PW |
||
+IN | 1 | - | - | I | Noninverting input |
+IN A | - | 3 | 5 | I | Noninverting input, channel A |
+IN B | - | 5 | 7 | I | Noninverting input, channel B |
+IN C | - | - | 9 | I | Noninverting input, channel C |
+IN D | - | - | 11 | I | Noninverting input, channel D |
-IN | 3 | - | - | I | Inverting input |
-IN A | - | 2 | 4 | I | Inverting input, channel A |
-IN B | - | 6 | 6 | I | Inverting input, channel B |
-IN C | - | - | 8 | I | Inverting input, channel C |
-IN D | - | - | 10 | I | Inverting input, channel D |
OUT | 4 | - | - | O | Output |
OUT A | - | 1 | 2 | O | Output, channel A |
OUT B | - | 7 | 1 | O | Output, channel B |
OUT C | - | - | 14 | O | Output, channel C |
OUT D | - | - | 13 | O | Output, channel D |
V+ | 5 | 8 | 3 | P | Positive (highest) power supply |
V- | 2 | 4 | 12 | P | Negative (lowest) power supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Differential Input Voltage | ±Supply Voltage | |||
Voltage on any pin (referred to V− pin) | 5.5 | V | ||
Soldering Information | ||||
Infrared or Convection (20 sec) | 235 | °C | ||
Junction Temperature (2) | 150 | °C | ||
Storage temperature, Tstg | −65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±800 | V |
Machine model | ±120 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage | 2.7 | 5 | V | |
Temperature Range (2) | −40 | 85 | °C |
THERMAL METRIC(1) | LMV331-N | LMV339-N | LMV393-N | UNIT | ||||
---|---|---|---|---|---|---|---|---|
DCK | DBV | D | PW | D | DGK | |||
5 PINS | 5 PINS | 14 PINS | 14 PINS | 8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 478 | 265 | 145 | 155 | 190 | 23 | °C/W |
PARAMETER | TEST CONDITIONS | MIN (1) |
TYP (2) |
MAX (1) |
UNIT | |
---|---|---|---|---|---|---|
VOS | Input Offset Voltage | 1.7 | 7 | mV | ||
TCVOS | Input Offset Voltage Average Drift | At the temperature extremes | 5 | µV/°C | ||
IB | Input Bias Current | 10 | 250 | nA | ||
At the temperature extremes | 400 | |||||
IOS | Input Offset Current | 5 | 50 | nA | ||
At the temperature extremes | 150 | |||||
VCM | Input Voltage Range | −0.1 | V | |||
2.0 | V | |||||
VSAT | Saturation Voltage | ISINK ≤ 1 mA | 120 | mV | ||
IO | Output Sink Current | VO ≤ 1.5V | 5 | 23 | mA | |
IS | Supply Current | LMV331-N | 40 | 100 | µA | |
LMV393-N Both Comparators |
70 | 140 | µA | |||
LMV339-N All four Comparators |
140 | 200 | µA | |||
Output Leakage Current | .003 | µA | ||||
At the temperature extremes | 1 |
PARAMETER | TEST CONDITIONS | MIN (1) |
TYP (2) |
MAX (1) |
UNIT | |
---|---|---|---|---|---|---|
tPHL | Propagation Delay (High to Low) | Input Overdrive = 10 mV | 1000 | ns | ||
Input Overdrive = 100 mV | 350 | ns | ||||
tPLH | Propagation Delay (Low to High) | Input Overdrive = 10 mV | 500 | ns | ||
Input Overdrive = 100 mV | 400 | ns |
PARAMETER | TEST CONDITIONS | MIN (1) |
TYP (2) |
MAX (1) |
UNIT | |
---|---|---|---|---|---|---|
VOS | Input Offset Voltage | 1.7 | 7 | mV | ||
At the temperature extremes | 9 | |||||
TCVOS | Input Offset Voltage Average Drift | 5 | µV/°C | |||
IB | Input Bias Current | 25 | 250 | nA | ||
At the temperature extremes | 400 | |||||
IOS | Input Offset Current | 2 | 50 | nA | ||
At the temperature extremes | 150 | |||||
VCM | Input Voltage Range | −0.1 | V | |||
4.2 | V | |||||
AV | Voltage Gain | 20 | 50 | V/mV | ||
Vsat | Saturation Voltage | ISINK ≤ 4 mA | 200 | 400 | mV | |
At the temperature extremes | 700 | |||||
IO | Output Sink Current | VO ≤ 1.5V | 84 | 10 | mA | |
IS | Supply Current | LMV331-N | 60 | 120 | µA | |
At the temperature extremes | 150 | |||||
LMV393-N Both Comparators |
100 | 200 | µA | |||
At the temperature extremes | 250 | |||||
LMV339-N All four Comparators |
170 | 300 |
µA | |||
At the temperature extremes | 350 | |||||
Output Leakage Current | .003 | µA | ||||
At the temperature extremes | 1 |
PARAMETER | TEST CONDITIONS | MIN (1) |
TYP (2) |
MAX (1) |
UNIT | |
---|---|---|---|---|---|---|
tPHL | Propagation Delay (High to Low) | Input Overdrive = 10 mV | 600 | ns | ||
Input Overdrive = 100 mV | 200 | ns | ||||
tPLH | Propagation Delay (Low to High) | Input Overdrive = 10 mV | 450 | ns | ||
Input Overdrive = 100 mV | 300 | ns |
The LMV331-N/393-N/339-N comparators features a supply voltage range of 2.7 V to 5 V with a low supply current of 55 μA/channel with propagation delays as low as 200ns. They are avaialble in small, space-saving packages, which makes these comparators versatile for use in a wide range of applications, from portable to industrial. The open collector output configuration allows the device to be used in wired-OR configurations, such as a window comparators.
The output of the LMV331-N/393-N/339-N series is the uncommitted collector of a grounded-emitter NPN output transistor, which requires a pull-up resistor to a positive supply voltage for the output to switch properly. Many collectors can be tied together to provide an output OR’ing function. An output pull-up resistor can be connected to any available power supply voltage within the permitted V+ supply voltage range. The output pull-up resistor should be chosen high enough so as to avoid excessive power dissipation yet low enough to supply enough drive to switch whatever load circuitry is used on the comparator output. On the LMV331-N/393-N/339-N the pull-up resistor should range between 1 k to 10 kΩ.
The LMV331-N/393-N/339-N has a typical input common mode voltage range of −0.1V below the ground to 0.8V below Vcc.
A basic comparator circuit is used for converting analog signals to a digital output.
The output is HIGH when the voltage on the non-inverting (+IN) input is greater than the inverting (-IN) input.
The output is LOW when the voltage on the non-inverting (+IN) input is less than the inverting (-IN) input.
The inverting input (-IN) is also commonly referred to as the "reference" or "VREF" input.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The comparator compares the input voltage (VIN) at the non-inverting pin to the reference voltage (VREF) at the inverting pin. If VIN is less than VREF, the output voltage (VO) is at the saturation voltage. On the other hand, if VIN is greater than VREF, the output voltage (VO) is at VCC.
The basic comparator configuration may oscillate or produce a noisy output if the applied differential input voltage is near the comparator's offset voltage. This usually happens when the input signal is moving very slowly across the switching threshold of the comparator. This problem can be prevented by the addition of hysteresis or positive feedback.
The inverting comparator with hysteresis requires a three resistor network that are referenced to the supply voltage VCC of the comparator. When Vin at the inverting input is less than Va, the voltage at the non-inverting node of the comparator (Vin < Va), the output voltage is high (for simplicity assume VO switches as high as VCC). The three network resistors can be represented as R1//R3 in series with R2. The lower input trip voltage Va1 is defined as:
When Vin is greater than Va (Vin > Va), the output voltage is low very close to ground. In this case the three network resistors can be presented as R2//R3 in series with R1. The upper trip voltage Va2 is defined as:
The total hysteresis provided by the network is defined as:
To assure that the comparator will always switch fully to VCC and not be pulled down by the load the resistors values should be chosen as follow:
Non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (Vref) at the inverting input. When Vin is low, the output is also low. For the output to switch from low to high, Vin must rise up to Vin1 where Vin1 is calculated by:
When Vin is high, the output is also high. To make the comparator switch back to its low state, Vin must equal Vref before VA will again equal Vref. Vin can be calculated by:
The hysteresis of this circuit is the difference between Vin1 and Vin2.
By the inherit nature of an open-collector comparator, the outputs of several comparators can be tied together with a shared pull-up resistor to VCC. If one or more of the comparators outputs goes low, the output VO will go low.
The output of the comparator is capable of driving CMOS and TTL Logic circuits. The pull-up resistor may be pulled-up to any voltage equal to, or less than the supply voltage on V+. However, it must not be pulled-up to a voltage higher than V+.
The comparator can be used as three input AND gate. The operation of the gate is as follows:
The resistor divider at the inverting input establishes a reference voltage at that node. The non-inverting input is the sum of the voltages at the inputs divided by the voltage dividers. The output will go high only when all three inputs are high, casing the voltage at the non-inverting input to go above that at inverting input. The circuit values shown work for a 0 equal to ground and a 1 equal to 5 V.
The resistor values can be altered if different logic levels are desired. If more inputs are required, diodes are recommended to improve the voltage margin when all but one of the inputs are high.
A three input OR gate is achieved from the basic AND gate simply by increasing the resistor value connected from the inverting input to Vcc, thereby reducing the reference voltage.
A logic 1 at any of the inputs will produce a logic 1 at the output.
Extra logic inputs may be added by ORing the input with multiple diodes.
Comparators are ideal for oscillator applications. This square wave generator uses the minimum number of components. The output frequency is set by the RC time constant of the capacitor C1 and the resistor in the negative feedback R4. The maximum frequency is limited only by the large signal propagation delay of the comparator in addition to any capacitive loading at the output, which would degrade the output slew rate.
To analyze the circuit, assume that the output is initially high. For this to be true, the voltage at the inverting input Vc has to be less than the voltage at the non-inverting input Va. For Vc to be low, the capacitor C1 has to be discharged and will charge up through the negative feedback resistor R4. When it has charged up to value equal to the voltage at the positive input Va1, the comparator output will switch.
Va1 will be given by:
If:
Then:
When the output switches to ground, the value of Va is reduced by the hysteresis network to a value given by:
Capacitor C1 must now discharge through R4 towards ground. The output will return to its high state when the voltage across the capacitor has discharged to a value equal to Va2.
For the circuit shown, the period for one cycle of oscillation will be twice the time it takes for a single RC circuit to charge up to one half of its final value. The time to charge the capacitor can be calculated from:
Where Vmax is the max applied potential across the capacitor = (2VCC/3)
and VC = Vmax/2 = VCC/3
One period will be given by:
or calculating the exponential gives:
Resistors R3 and R4 must be at least two times larger than R5 to ensure that VO will go all the way up to VCC in the high state. The frequency stability of this circuit should strictly be a function of the external components.
A simple yet very stable oscillator that generates a clock for slower digital systems can be obtained by using a resonator as the feedback element. It is similar to the squarewave oscillator, except that the positive feedback is obtained through a quartz crystal. The circuit oscillates when the transmission through the crystal is at a maximum, so the crystal in its series-resonant mode.
The value of R1 and R2 are equal so that the comparator will switch symmetrically about +VCC/2. The RC constant of R3 and C1 is set to be several times greater than the period of the oscillating frequency, insuring a 50% duty cycle by maintaining a DC voltage at the inverting input equal to the absolute average of the output waveform.
When specifying the crystal, be sure to order series resonant with the desired temperature coefficient.
The pulse generator with variable duty cycle is just a minor modification of the basic square wave generator. Providing a separate charge and discharge path for capacitor C1generates a variable duty cycle. One path, through R2 and D2 will charge the capacitor and set the pulse width (t1). The other path, R1 and D1 will discharge the capacitor and set the time between pulses (t2).
By varying resistor R1, the time between pulses of the generator can be changed without changing the pulse width. Similarly, by varying R2, the pulse width will be altered without affecting the time between pulses. Both controls will change the frequency of the generator. The pulse width and time between pulses can be found from:
Solving these equations for t1 and t2
These terms will have a slight error due to the fact that Vmax is not exactly equal to 2/3 VCC but is actually reduced by the diode drop to:
Positive peak detector is basically the comparator operated as a unit gain follower with a large holding capacitor from the output to ground. Additional transistor is added to the output to provide a low impedance current source. When the output of the comparator goes high, current is passed through the transistor to charge up the capacitor. The only discharge path will be the 1-MΩ resistor shunting C1 and any load that is connected to the output. The decay time can be altered simply by changing the 1-MΩ resistor. The output should be used through a high impedance follower to a avoid loading the output of the peak detector.
For the negative detector, the output transistor of the comparator acts as a low impedance current sink. The only discharge path will be the 1-MΩ resistor and any load impedance used. Decay time is changed by varying the 1-MΩ resistor.