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Data Sheet
LMX1205 Low-Noise, High-Frequency JESD Buffer/Multiplier/Divider
1 Features
- Output frequency: 300MHz to 12.8GHz
- Noiseless adjustable input delay
up to 60ps with 1.1ps resolution
- Individual adjustable output
delays up to 55ps with 0.9ps resolution
- Ultra-low noise
- Noise floor: –159dBc/Hz at 6GHz output
- Additive jitter (DC to fCLK): 36fs
- Additive jitter (100Hz to
100MHz): 10fs
- Four high-frequency clocks with corresponding SYSREF outputs
- Shared divide by 1 (Bypass), 2, 3, 4, 5, 6, 7, and
8
- Shared programmable multiplier x2, x3, x4, x5, x6, x7
and x8
- LOGICLK output with corresponding SYSREF output
- On separate divide bank
- 1, 2, 4 pre-divider
- 1 (bypass), 2, …, 1023 post divider
- Second logic clock option with additional divider 1, 2, 4 & 8
- Six programmable output power levels
- Synchronized SYSREF clock outputs
- 508 delay step adjustments of less than 2.5ps at
12.8GHz
- Generator, repeater and repeater retime modes
- Windowing feature for
SYSREFREQ pins to optimize timing
- SYNC feature to all divides and multiple devices
- Operating voltage: 2.5V
- Operating temperature: –40ºC to +85ºC
2 Applications
- Test & Measurement:
- Aerospace & Defense:
- General Purpose:
- Data converter
clocking
- Clock buffer distribution
/ division
