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  • LMX2492/LMX2492-Q1 14 GHz Low Noise Fractional N PLL with Ramp/Chirp Generation

    • SNAS624B March   2014  – May 2015 LMX2492 , LMX2492-Q1

      PRODUCTION DATA.  

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  • LMX2492/LMX2492-Q1 14 GHz Low Noise Fractional N PLL with Ramp/Chirp Generation
  1. 1 Features
  2. 2  Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Storage Conditions
    3. 7.3 ESD Ratings
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Timing Requirements, Programming Interface (CLK, DATA, LE)
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Feature Description
      1. 8.3.1  OSCin Input
      2. 8.3.2  OSCin Doubler
      3. 8.3.3  R Divider
      4. 8.3.4  PLL N Divider
      5. 8.3.5  Fractional Circuitry
      6. 8.3.6  PLL Phase Detector and Charge Pump
      7. 8.3.7  External Loop Filter
      8. 8.3.8  Fastlock and Cycle Slip Reduction
      9. 8.3.9  Lock Detect and Charge Pump Voltage Monitor
        1. 8.3.9.1 Charge Pump Voltage Monitor
        2. 8.3.9.2 Digital Lock Detect
      10. 8.3.10 FSK/PSK Modulation
      11. 8.3.11 Ramping Functions
        1. 8.3.11.1 Ramp Count
        2. 8.3.11.2 Ramp Comparators and Ramp Limits
      12. 8.3.12 Power on Reset (POR)
    4. 8.4  Device Functional Modes
      1. 8.4.1 Continuous Frequency Generator
        1. 8.4.1.1 Integer Mode Operation
        2. 8.4.1.2 Fractional Mode Operation
      2. 8.4.2 Modulated Waveform Generator
    5. 8.5  Programming
      1. 8.5.1 Loading Registers
    6. 8.6  Register Map
    7. 8.7  Register Field Descriptions
      1. 8.7.1 POWERDOWN and Reset Fields
      2. 8.7.2 Dividers and Fractional Controls
        1. 8.7.2.1 Speed Up Controls (Cycle Slip Reduction and Fastlock)
    8. 8.8  Lock Detect and Charge Pump Monitoring
    9. 8.9  TRIG1,TRIG2,MOD, and MUXout Pins
    10. 8.10 Ramping Functions
    11. 8.11 Individual Ramp Controls
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plot - Sawtooth Waveform Example
      4. 9.2.4 Application Performance Plot - Flat Top Triangle Waveform
      5. 9.2.5 Applications Performance Plot -- Complex Triggered Ramp
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RTW|24
    • MPQF167C
Thermal pad, mechanical data (Package|Pins)
  • RTW|24
    • QFND450A
Orderable Information
  • snas624b_oa
  • snas624b_pm
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DATA SHEET

LMX2492/LMX2492-Q1 14 GHz Low Noise Fractional N PLL with Ramp/Chirp Generation

1 Features

  • -227 dBc/Hz Normalized PLL Noise
  • 500 MHz - 14 GHz Wideband PLL
  • 3.15 - 5.25 V Charge Pump PLL Supply
  • Versatile Ramp / Chirp Generation
  • 200 MHz Max Phase Detector Frequency
  • FSK / PSK Modulation Pin
  • Digital Lock Detect
  • Single 3.3 V Supply Capability
  • Automotive 125°C Q100 Grade 1 Qualification
  • Non-Automotive (LMX2492) Option

2 Applications

  • Automotive FMCW Radar
  • Military Radar
  • Microwave Backhaul
  • Test and Measurement
  • Satellite Communications
  • Wireless Infrastructure
  • Sampling Clock for High Speed ADC/DAC

3 Description

The LMX2492/92-Q1 is a low noise 14 GHz wideband delta-sigma fractional N PLL with ramp and chirp generation. It consists of a phase frequency detector, programmable charge pump, and high frequency input for the external VCO. The LMX2492/92-Q1 supports a broad and flexible class of ramping capabilities, including FSK, PSK, and configurable piecewise linear FM modulation profiles of up to 8 segments. It supports fine PLL resolution and fast ramp with up to a 200 MHz phase detector rate. The LMX2492/92-Q1 allows any of its registers to be read back. The LMX2492/92-Q1 can operate with a single 3.3 V supply. Moreover, supporting up to 5.25 V charge pump can eliminate the need of external amplifier, leading to a simpler solution with improved phase noise performance.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)
LMX2492-Q1RTW WQFN (24) 4.00 mm x 4.00 mm
LMX2492RTW WQFN (24) 4.00 mm x 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

LMX2492 LMX2492-Q1 sch_main_snas624.gif

5 Revision History

Changes from A Revision (June 2014) to B Revision

  • Changed Changed CLK, DATA, and LE to right Input/Output Format Go
  • Changed terminal to pin Go
  • Changed Same specs, but new format tables for storage and ESD Ratings Go
  • Changed TYP to NOM Go
  • Added Added comment for lower voltage operation.Go
  • Changed Fixed Diagram. A14 is hightest bitGo
  • Added note in Applications and Implementation section Go

Changes from * Revision (March 2014) to A Revision

  • Changed from 35 to 10Go
  • Changed from 10 to 4Go
  • Changed from 10 to 4Go
  • Changed from 25 to 10 Go
  • Changed from 25 t o10Go

6 Pin Configuration and Functions

24 Pin WQFN
RTW Package
(Top View)
LMX2492 LMX2492-Q1 po_snas624.gif

Pin Functions

PIN I/O DESCRIPTION
NUMBER NAME
0 DAP GND Die Attach Pad. Connect to PCB ground plane.
1 GND GND Ground for charge pump.
2,3 GND GND Ground for Fin Buffer
4,5 Fin
Fin*		 Input Complimentary high frequency input pins. Should be AC coupled. If driving single-ended, impedance as seen from Fin and Fin* pins looking outwards from the part should be roughly the same.
6 Vcc Supply Power Supply for Fin Buffer
7 Vcc Supply Supply for On-chip LDOs
8 Vcc Supply Supply for OSCin Buffer
9 OSCin Input Reference Frequency Input
10 GND/
OSCin*		 GND/Input Complimentary input for OSCin.
If not used, it is recommended to match the termination as seen from the OSCin terminal looking outwards. However, this may also be grounded as well.
11 GND GND Ground for OSCin Buffer
12 MOD Input/Output Multiplexed Pin for Ramp Triggers, FSK/PSK Modulation, FastLock, Readback, and Diagnostics.
13 CE Input Chip Enable
14 CLK Input Serial Programming Clock.
15 DATA Input Serial Programming Data
16 LE Input Serial Programming Latch Enable
17 MUXout Input/Output Multiplexed Pin for Ramp Triggers, FSK/PSK Modulation, FastLock, Readback, and Diagnostics.
18 Vcc Supply Supply for delta sigma engine.
19 Vcc Supply Supply for general circuitry.
20 TRIG1 Input/Output Multiplexed Pin for Ramp Triggers, FSK/PSK Modulation, FastLock, Readback, and Diagnostics.
21 TRIG2 Input/Output Multiplexed Pin for Ramp Triggers, FSK/PSK Modulation, FastLock, Readback, and Diagnostics.
22 Vcp Supply Power Supply for the charge pump.
23 Rset NC No connect.
24 CPout Output Charge Pump Output

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Vcp Supply voltage for charge pump Vcc 5.5 V
CPout Charge pump output pin -0.3 Vcp V
Vcc All Vcc pins -0.3 3.6 V
Others All other I/O pins -0.3 Vcc + 0.3 V
TSolder Lead temperature (solder 4 seconds) 260 °C
TJunction Junction temperature 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Storage Conditions

applicable before the DMD is installed in the final product
MIN MAX UNIT
Tstg DMD storage temperature -65 150 °C
MSL Moisture sensitivity level 3 n/a

7.3 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
PARAMETER DEVICE MIN NOM MAX UNIT
Vcc PLL supply voltage 3.15 3.3 3.45 V
Vcp Charge pump supply voltage Vcc 5.25 V
TA Ambient temperature LMX2492 -40 85 °C
LMX2492-Q1 -40 125
TJ Junction temperature LMX2492 -40 125 °C
LMX2492-Q1 -40 135

7.5 Thermal Information

THERMAL METRIC(1) LMX2492 RTW (WQFN )
24 PINS		 UNIT
RθJA Junction-to-ambient thermal resistance 39.4 °C/W
RθJC Junction-to-case thermal resistance 7.1
ψJB Junction-to-board characterization parameter 20
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.6 Electrical Characteristics

(3.15 V ≤ Vcc ≤ 3.45 V. Vcc ≤Vcp ≤5.25 V. Typical values are at Vcc = Vcp = 3.3 V, 25 °C.
-40°C ≤ TA ≤ 85 °C for the LMX2492 and -40°C ≤ TA ≤ 125 °C for the LMX2492-Q1 ; except as specified.)
PARAMETER CONDITIONS MIN TYP MAX UNIT
Icc Current Consumption All Vcc Pins Fpd = 10 MHz 45 mA
Fpd = 100 MHz 50
Fpd = 200 MHz 55
Vcp Pin Kpd = 0.1 mA 2
Kpd = 1.6 mA 10
Kpd = 3.1 mA 19
IccPD Current POWERDOWN 3
fOSCin Frequency for OSCin terminal OSC_DIFFR=0, Doubler Disabled 10 600 MHz
OSC_DIFFR=0, Doubler Enabled 10 300
OSC_DIFFR=1, Doubler Disabled 10 1200
OSC_DIFFR=1, Doubler Enabled 10 600
vOSCin Voltage for OSCin Pin(1) LMX2492-Q1 Version Only
Single Ended XO
30 MHz ≤ fOSCin ≤ 100 MHz		 0.24 Vcc-0.5 Vpp
All Other Cases 0.5 Vcc-0.5
fFin Frequency for FinPin(4) 500 14000 MHz
pFin Power for Fin Pin Single-Ended Operation -5 5 dBm
fPD Phase Detector Frequency 200 MHz
PN1Hz PLL Figure of Merit(2) -227 dBc/Hz
PN10kHz Normalized PLL 1/f Noise(2) Normalized to 10 kHz offset for a 1 GHz carrier. -120 dBc/Hz
ICPoutTRI Charge Pump Leakage Tri-state Leakage 10 nA
ICPoutMM Charge Pump Mismatch(3) VCPout = Vcp / 2 5 %
ICPout Charge Pump Current VCPout = Vcp / 2 CPG=1X 0.1 mA
…
CPG=31X 3.1
LOGIC OUTPUT TERMINALS (MUXout,TRIG1,TRIG2,MOD)
VOH Output High Voltage 0.8 x Vcc Vcc V
VOL Output Low Voltage 0 0.2 x Vcc V
LOGIC INPUT TERMINALS (CE,CLK,DATA,LE,MUXout,TRIG1,TRIG2,MOD)
VIH Input High Voltage 1.4 Vcc V
VIL Input Low Voltage 0 0.6 V
IIH Input Leakage -5 1 5 uA
TCELOW Chip enable Low Time 5 us
TCEHIGH Chip enable High Time 5 us
(1) For optimal phase noise performance, a slew rate of at least 3 V/ns is recommended
(2) PLL Noise Metrics are measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an infinite loop bandwidth as:
PLL_Total = 10×log( 10PLL_Flat/10 + 10PLL_Flicker(Offset)/10)
PLL_Flat = PN1Hz + 20×log(N) + 10×log(Fpd/1Hz)
PLL_Flicker = PN10kHz - 10×log(Offset/10kHz) + 20×log(Fvco/1GHz)
(3) Charge pump mismatch varies as a function of charge pump voltage. Consult typical performance characteristics to see this variation.
(4) Tested to 13.5 GHz, Guaranteed to 14 GHz by characterization

7.7 Timing Requirements, Programming Interface (CLK, DATA, LE)

MIN NOM MAX UNIT
TCE Clock To LE Low Time 10 ns
TCS Data to Clock Setup Time 4 ns
TCH Data to Clock Hold Time 4 ns
TCWH Clock Pulse Width High 10 ns
TCWL Clock Pulse Width Low 10 ns
TCES Enable to Clock Setup Time 10 ns
TEWH Enable Pulse Width High 10 ns
LMX2492 LMX2492-Q1 td_snas624.gifFigure 1. Serial Data Input Timing

There are several other considerations for programming:

  • The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift register to an actual counter.
  • If no LE signal is given after the last data bit and the clock is kept toggling, then these bits will be read into the next lower register. This eliminates the need to send the address each time.
  • A slew rate of at least 30 V/us is recommended for the CLK, DATA, and LE signals
  • Timing specifications also apply to readback. Readback can be done through the MUXout, TRIG1, TRIG2, or MOD terminals.

7.8 Typical Characteristics

LMX2492 LMX2492-Q1 tc03_cpout3V_snas624.png
For a charge pump supply of 3.3 V, optimal performance is for a typical charge pump output voltage between 0.5 and 2.8 volts.
Figure 2. Charge Pump Current for Vcp = 3.3 V
LMX2492 LMX2492-Q1 tc04_cpout5V_snas624.png
For a charge pump supply voltage of 5 volts or higher, optimal performance is typically for a charge pump output voltage between 0.5 and 4.5 volts.
Figure 3. Charge Pump Current for Vcp = 5.5 V
LMX2492 LMX2492-Q1 tc02_sensitivity_snas624.png
Typical value of lowest power level as a function of frequency. Design to electrical specifications for input sensitivity, not typical performance graphs.
Figure 4. Fin Input Sensitivity
LMX2492 LMX2492-Q1 tc01_pnoise_snas624.png
This plot is for a phase detector of 100 MHz, 2 MHz loop bandwidth, and VCO at 9600 MHz. However, the plot shown is the divide by 2 port at 4800 MHz. The input was a 100 MHz Wenzel Oscillator. The model shows this phase noise has a figure of merit of -227 dBc/Hz and a normalized 1/f noise of -120.5 dBc/Hz. The charge pump supply was 5 V and the charge pump output voltage was 1.34 V.
Figure 5. LMX2492/92-Q1 Phase Noise for Fpd =100 MHz, Fvco = 9600 MHz/2

 
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