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  • LP5922 2-A Low-Noise, Adjustable LDO With Low Input- and Output-Voltage Capability

    • SNVSAG0A November   2016  – February 2017 LP5922

      PRODUCTION DATA.  

  • CONTENTS
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  • LP5922 2-A Low-Noise, Adjustable LDO With Low Input- and Output-Voltage Capability
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Input and Output Capacitors
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage
      2. 7.3.2 Enable
      3. 7.3.3 Output Automatic Discharge
      4. 7.3.4 Programmable Soft Start and Noise Reduction
      5. 7.3.5 Internal Current Limit
      6. 7.3.6 Thermal Overload Protection
      7. 7.3.7 Power Good Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable (EN)
      2. 7.4.2 Undervoltage Lockout (UVLO)
      3. 7.4.3 Minimum Operating Input Voltage
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  External Capacitors
        3. 8.2.2.3  Input Capacitor, CIN
        4. 8.2.2.4  Output Capacitor, COUT
        5. 8.2.2.5  Soft-Start and Noise-Reduction Capacitor, CSS/NR
        6. 8.2.2.6  Feed-Forward Capacitor, CFF
        7. 8.2.2.7  No-Load Stability
        8. 8.2.2.8  Power Dissipation
        9. 8.2.2.9  Estimating Junction Temperature
        10. 8.2.2.10 Recommended Continuous Operating Area
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DSC|10
    • MPDS239E
Thermal pad, mechanical data (Package|Pins)
  • DSC|10
    • QFND232J
Orderable Information
  • snvsag0a_oa
  • snvsag0a_pm
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DATA SHEET

LP5922 2-A Low-Noise, Adjustable LDO With Low Input- and Output-Voltage Capability

1 Features

  • Wide Input Voltage Range: 1.3 V to 6 V
  • Low VIN Voltage Without Extra Bias Voltage
  • Adjustable Output Voltage: 0.5 V to 5 V
  • Low Dropout: 200 mV at 2-A Load
  • Low Output Voltage Noise: 25 μVRMS
  • Output Current: 2 A
  • –40˚C to +125°C Operating Junction Temperature
  • Programmable Soft Start Limits Inrush Current
  • 3-mm × 3-mm × 0.75-mm 10-Pin WSON Package
  • Thermal-Overload and Short-Circuit Protection
  • Output Voltage Tolerance: ±1.5%
  • Shutdown Supply Current : 0.1 μA
  • PSRR: 70 dB at 1 kHz
  • Power Good Output
  • Create a Custom Design Using the LP5922 With the WEBENCH® Power Designer

2 Applications

  • Space-Constrained Applications
  • Noise- and Ripple-Sensitive High Current Analog or RF Systems
  • Target Sectors
    • Medical, Test and Measurement Equipment
    • Portable and Consumer electronics
    • Telecom and Networking Cards
    • Wireless Infrastructure
    • Industrial Applications
  • Typical Systems
    • Radio Transceivers, Power Amplifiers, PLL/Synthesizer, Clocking, VCO, GPRS, 3G Modules, FPGAs, DSP, GPUs, and others

3 Description

The LP5922 is 2-A low dropout (LDO) linear regulator with 200-mV typical dropout voltage at maximum current levels. The LP5922 device can operate from a voltage rail down to 1.3 V without additional bias supply. System efficiency is maximized and power dissipation minimized by the low dropout and low VIN capability. The device also features low quiescent current and very low shutdown current.

The LP5922 device was designed to have high PSRR and low output noise to support sensitive analog applications without additional filtering. The output noise can be reduced even further by implementing a small capacitor on the SS/NR pin.

The output voltage is adjustable from 0.5 V to 5 V by an external resistor divider. Enable pin, adjustable soft start and optional Power Good features help with system power sequencing. Inrush current is controlled with the soft start and the device has short circuit and thermal protections.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LP5922 WSON (10) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

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Simplified Schematic

LP5922 simp_schem_snvsag0.gif

PSRR

LP5922 D014_SNVSAG0.gif

4 Revision History

Changes from * Revision (November 2016) to A Revision

  • Added links to WEBENCH Go
  • Changed load transients test conditions from "VOUT = 3.3 V" to "VOUT = 2.8 V" and "tRISE = tFALL = 1 V/μs" to "tRISE = tFALL = 1 A/μs"Go
  • Changed "tfall = 1 V/µs" to "tfall = 1 A/µs" in legend to Figure 9 Go
  • Changed scope shot in Figure 10 (was duplicate of Fig 9) and changed condition from "tfall = 1 V/µs" to "tfall = 1 A/µs" Go
  • Changed tfall = 1 V/μs" to "tRISE =tFALL = 5 µs" in Figure 11 conditionsGo
  • Added Custom Design With WEBENCH Tools subsection Go

5 Pin Configuration and Functions

DSC Package
10-Pin WSON With Thermal Pad
Top View
LP5922 pinout_snvsag0.gif

Pin Functions

PIN I/O DESCRIPTION
NUMBER NAME
1 OUT O Regulated output voltage, connect directly to pin 2
2 OUT O Regulated output voltage, connect directly to pin 1
3 FB I Voltage feedback input to the internal error amplifier
4 GND Ground Ground; connect to device pin 8.
5 PG O Power Good to indicate the status of output voltage. Requires an external pullup resistor. When PG pin voltage is high the output voltage is considered good.
6 EN I Enable
7 SS/NR I/O Soft-start and noise reduction pin
8 GND Ground Ground —connect to device pin 4.
9 IN I Supply voltage input — connect directly to pin 10.
10 IN I Supply voltage input —connect directly to pin 9.
Exposed pad Thermal Pad — The exposed thermal pad on the bottom of the package must be connected to a copper area under the package on the PCB. Connect to ground potential. Do not connect to any potential other than the same ground potential seen at device pins 4 and 8 (GND). See Power Dissipation for more information.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
IN pin voltage, VIN –0.3 7 V
OUT pin voltage, VOUT See(3)
EN pin voltage, VEN –0.3 7 V
PG pin voltage, VPG –0.3 7 V
SS/NR pin voltage, VSS/NR –0.3 3.6 V
FB pin voltage, VFB –0.3 3.6 V
Junction temperature, TJ 150 °C
Continuous power dissipation(4) Internally limited
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pin.
(3) Absolute maximum VOUT is the lesser of VIN + 0.3 V, or 7 V.
(4) Internal thermal shutdown circuitry protects the device from permanent damage.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input voltage, VIN 1.3 6 V
Output voltage, VOUT 0.5 5 V
FB voltage, VFB 0.5 V
EN input voltage, VEN 0 VIN V
Recommended load current, IL 0 2 A
Operating junction temperature, TJ-MAX-OP –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) LP5922 UNIT
DSC (WSON)
10 PINS
RθJA(2) Junction-to-ambient thermal resistance, High K 49.5(3) °C/W
RθJC(top) Junction-to-case (top) thermal resistance 38.2 °C/W
RθJB Junction-to-board thermal resistance 24.0 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 24.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.0 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(3) The PCB for the WSON/DSC package RθJA includes four (4) thermal vias, in a 2 × 2 array, under the exposed thermal pad per EIA/JEDEC JESD51-5.

6.5 Electrical Characteristics

VIN = VOUT(NOM) + 0.5 V or 1.3 V, whichever is greater; VEN = 1.2 V, CIN = 22 μF, COUT = 22 μF, OUT connected to 50 Ω to GND, VFB = 0.5 V, CSS/NR = 0.12 µF, CFF = 0.01 µF, and PG pin pulled up to VIN by 100-kΩ resistor (unless otherwise noted).(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VIN Input voltage range 1.3 6 V
UVLO Undervoltage lock-out threshold VIN Rising (↑) until output is ON 1.2 1.25 V
ΔUVLO UVLO hysteresis VIN Falling (↓) from UVLO threshold until output is OFF 160 mV
OUTPUT VOLTAGE AND REGULATION
VOUT Output voltage range 0.5 5 V
ΔVOUT Line regulation IOUT = 5 mA, 1.3 V ≤ VIN ≤ 6 V 0.02 %/V
Load regulation 5 mA ≤ IOUT ≤ 2 A 0.1 %/A
VDO Dropout voltage(4) VIN = 1.4 V, IOUT = 2 A 220 400 mV
VIN = 2.5 V, IOUT = 2 A 100 180
VIN = 5.3 V, IOUT = 2 A 90 160
FB
VFB FB voltage IOUT = 5 mA to 2 A 492.5 500 507.5 mV
IFB FB pin input current VFB = 0.5 V –100 100 nA
CURRENT LEVELS
IL Maximum load current VIN ≥ 1.3 V 2 A
ISC Short-circuit current limit(5) 2.2 3 3.8 A
IGND Ground-current minimum load(7) VIN = 6 V, IOUT = 0 mA 0.7 mA
Ground-current maximum load(7) VIN = 1.3 V, IOUT = 2 A 1 4
IGND(SD) Shutdown current(6) VIN = 6 V, VEN = 0 V, VPG = 0 V 0.1 15 µA
VIN to VOUT RIPPLE REJECTION (9)
PSRR Power-supply rejection ratio VIN ≥ 1.4 V, ƒ = 1 kHz, IOUT = 2 A 70 dB
VIN ≥ 1.4 V, ƒ = 10 kHz, IOUT = 2 A 55
VIN ≥ 1.4 V, ƒ = 100 kHz, IOUT = 2 A 40
VIN ≥ 1.4 V, ƒ = 1 MHz, IOUT = 2 A 30
OUTPUT NOISE VOLTAGE
eN Noise voltage(9) VIN= 2.5 V, VOUT= 1.8 V
BW = 10 Hz to 100 kHz		 25 µVRMS
LOGIC INPUT THRESHOLDS
VIL(EN) EN pin low threshold VEN falling (↓) until output is OFF 0.35 V
VIH(EN) EN pin high threshold VEN rising (↑) until output is ON 1.2 V
IEN Input current at EN pin (8) VIN = 6 V, VEN = 6 V 3 µA
PGHTH PG high threshold (% of nominal VOUT) VOUT rising (↑) until PG goes high 94%
PGLTH PG low threshold (% of nominal VOUT) VOUT falling (↓) until PG goes low 90%
VOL(PG) PG pin low-level output voltage VOUT < PGLTH, sink current = 1 mA 400 mV
ILKG(PG) PG pin leakage current VOUT > PGHTH, VPG = 6 V 1 µA
SOFT START
ISS SS/NR pin charging current 6.2 µA
THERMAL SHUTDOWN
TSD Thermal shutdown temperature 165 °C
ΔTSD Thermal shutdown hysteresis 15 °C
TRANSITION CHARACTERISTICS
ΔVOUT Line transients ΔVIN = 0.5 V, VOUT = 2.8 V,
tRISE = tFALL = 5 μs		 3 mV
Load transients VOUT = 2.8 V, IOUT = 10 mA to 2 A to 10 mA
tRISE = tFALL = 1 A/μs		 25
RAD Output discharge pull-down resistance VEN = 0 V, VIN = 2.3 V 400 Ω
(1) All voltages are with respect to the GND pin.
(2) Minimum and maximum limits are design targeted limits over the junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
(3) CIN, COUT: Low-ESR surface-mount-ceramic capacitors (MLCCs) used in setting electrical characteristics.
(4) Dropout voltage is the voltage difference between the input and the output at which the FB voltage drops to 97% of its nominal value.
(5) Short-circuit current (ISC) is equivalent to current limit. To minimize thermal effects during testing, ISC is measured with VOUT pulled to 100 mV below its nominal voltage.
(6) Ground current in shutdown mode, IGND(SD), does NOT include current from PG pin.
(7) Ground current is defined here as the total current flowing to ground as a result of all voltages applied to the device
IGND = ( (IIN – IOUT) + IEN + ILKG(PG))
(8) There is a 2-MΩ resistor between EN and ground (pulldown) on the device.
(9) This specification is verified by design.

6.6 Input and Output Capacitors

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CIN Input capacitance(1) 22 µF
COUT Output capacitance VOUT ≤ 0.8 V 34 47 µF
VOUT > 0.8 V 15 22
(1) Typically input capacitance placed close to the device is in the same order as output capacitance. See also Input Capacitor, CIN.

6.7 Typical Characteristics

VIN = VOUT + 0.5 V, VEN = 1.2 V, CIN = 22 μF, COUT = 22 μF, OUT connected to 50 Ω to GND, VFB = 0.5 V, CSS/NR = 0.12 µF, CFF = 0.01 µF, and PG pin pulled up to VIN by 100-kΩ resistor and TJ = 25°C, unless otherwise stated.
LP5922 D007_SNVSAG0.gif
Figure 1. VEN Thresholds vs Input Voltage
LP5922 D008_SNVSAG0.gif
VOUT = 5 V VEN = VIN IOUT = 1 mA
Figure 3. Power Up
LP5922 D010_SNVSAG0.gif
VOUT = 5 V VEN = VIN IOUT = 1 mA
Figure 5. Power Down
LP5922 D012_SNVSAG0.gif
VOUT = 5 V IOUT = 1 mA
Figure 7. Power Down
LP5922 LoadTrUp_SNVSAG0.gif
VOUT = 2.8 V IOUT = 10 mA to 2 A trise = 1 A/µs
Figure 9. Load Transient Response
LP5922 LineTr_SNVSAG0.gif
VOUT = 2.8 V tRISE = tFALL = 5 µs
VIN = 3.3 V to 3.8 V to 3.3 V
Figure 11. Line Transient Response
LP5922 D014_SNVSAG0.gif
VIN = 5.5 V VOUT = 5 V
Figure 13. PSRR vs Frequency
LP5922 D017_SNVSAG0.gif
Figure 2. Ground Current vs Output Current
LP5922 D009_SNVSAG0.gif
VOUT = 5 V VEN = VIN IOUT = 2 A
Figure 4. Power Up
LP5922 D011_SNVSAG0.gif
VOUT = 5 V VEN = VIN IOUT = 2 A
Figure 6. Power Down
LP5922 D013_SNVSAG0.gif
VOUT = 5 V IOUT = 2 A
Figure 8. Power Down
LP5922 LoadTrDwn_SNVSAG0.gif
VOUT = 2.8 V IOUT = 2 A to 10 mA tFALL = 1 A/µs
Figure 10. Load Transient Response
LP5922 D015_SNVSAG0.gif
Figure 12. Dropout Voltage (VDO) vs Load Current
LP5922 D016_SNVSAG0.gif
VIN = 2.5 V VOUT = 1.8 V
Figure 14. Noise Density vs Frequency

 
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