Provides bidirectional voltage translation with no direction pin
Supports up to 100 MHz up translation and greater than 100 MHz down translation at ≤ 30-pF capacitive load and up to 40 MHz up or down translation at 50-pF capacitive load
Supports hot insertion
Allow bidirectional voltage level translation between
0.65 V ↔ 1.8 V, 2.5 V, 3.3 V, 5 V (RKS package
only)
0.95 V ↔ 1.8 V, 2.5 V, 3.3 V, 5 V
1.2 V ↔ 1.8 V, 2.5 V, 3.3 V, 5 V
1.8 V ↔ 2.5 V, 3.3 V, 5 V
2.5 V ↔ 3.3 V, 5 V
3.3 V ↔ 5 V
Low standby current
5-V tolerance I/O port to support TTL
Low ron provides less signal distortion
High-impedance I/O pins for EN = low
Flow-through pin-out for easy PCB trace routing
Latch-up performance exceeds 100 mA per JESD 17
–40°C to +125°C operating temperature range
Functional Block Diagram
2 Applications
GPIO, MDIO, PMBus, SMBus, SDIO,
UART, I2C, and other interfaces in telecom infrastructure