SLAS590P March 2009 – September 2020 MSP430F5513 , MSP430F5514 , MSP430F5515 , MSP430F5517 , MSP430F5519 , MSP430F5521 , MSP430F5522 , MSP430F5524 , MSP430F5525 , MSP430F5526 , MSP430F5527 , MSP430F5528 , MSP430F5529
PRODUCTION DATA
The Texas Instruments MSP430F55xx microcontrollers (MCUs) are part of the MSP430™ system control & communication family of ultra-low-power microcontrollers consists of several devices featuring peripheral sets targeted for a variety of applications. The architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. The microcontroller features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the devices to wake up from low-power modes to active mode in 3.5 µs (typical).
The MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 microcontrollers have integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 12-bit analog-to-digital converter (ADC), two USCIs, a hardware multiplier, DMA, an RTC module with alarm capabilities, and 63 I/O pins. The MSP430F5528, MSP430F5526, MSP430F5524, and MSP430F5522 microcontrollers include all of these peripherals but have 47 I/O pins.
The MSP430F5519, MSP430F5517, and MSP430F5515 microcontrollers have integrated USB and PHY supporting USB 2.0, four 16-bit timers, two USCIs, a hardware multiplier, DMA, an RTC module with alarm capabilities, and 63 I/O pins. The MSP430F5514 and MSP430FF5513 microcontrollers include all of these peripherals but have 47 I/O pins.
Typical applications include analog and digital sensor systems, data loggers, and others that require connectivity to various USB hosts.
The MSP430F55xx MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get your design started quickly. Development kits include the MSP430F5529 USB LaunchPad™ development kit and the MSP430F5529 experimenter’s board as well as the MSP-TS430PN80USB 80-pin target development board and the MSP-TS430RGC64USB 64-pin target development board. TI also provides free MSP430Ware™ software, which is available as a component of Code Composer Studio™ IDE desktop and cloud versions within TI Resource Explorer. The MSP430 MCUs are also supported by extensive online collateral, training, and online support through the TI E2E™ support forum.
For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.
PART NUMBER(1) | PACKAGE | BODY SIZE(2) |
---|---|---|
MSP430F5529IPN | LQFP (80) | 12 mm × 12 mm |
MSP430F5528IRGC | VQFN (64) | 9 mm × 9 mm |
MSP430F5528IYFF | DSBGA (64) | See Section 11 |
MSP430F5528IZXH | nFBGA (80) | 5 mm × 5 mm |
MSP430F5528IZQE(3) | MicroStar Junior™ BGA (80) | 5 mm × 5 mm |
Figure 4-1 shows the functional block diagram for the MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 devices in the PN package.
Figure 4-2 shows the functional block diagram for the MSP430F5528, MSP430F5526, MSP430F5524, and MSP430F5522 devices in the RGC, ZXH, and ZQE packages and for the MSP430F5528 device in the YFF package.
Figure 4-3 shows the functional block diagram for the MSP430F5519, MSP430F5517, and MSP430F5515 devices in the PN package.
Figure 4-4 shows the functional block diagram for the MSP430F5514 and MSP430F5513 devices in the RGC, ZXH, and ZQE packages.
Changes from revision O to revision P
Changes from May 1, 2019 to September 11, 2020
Changes from revision N to revision O
Changes from September 21, 2018 to April 30, 2019
Changes from revision M to revision N
Changes from November 3, 2015 to September 20, 2018
Changes from revision L to revision M
Changes from June 17, 2013 to November 2, 2015
The following table lists the changes to this data sheet from the initial release through revision L.
REVISION | DESCRIPTION |
---|---|
SLAS590L June 2013 |
Production release of F5226 and F5224 in YFF package. Section 1, Added note regarding pullup resistor on RST/NMI/SBWTDIO pin. Figure 1-6, Added ball-side view and changed top-side view. |
SLAS590K February 2013 | Section 1, Changed IERASE and IMERASE values. |
SLAS590J December 2012 |
Section 1, Added TYP test conditions Section 1, Added note (1) Section 1, Restored Flash erase currents to previous values (changed from TBD). |
SLAS590I August 2012 |
Changed MSP430F5528IYFF to Production Data. Section 1, Changed PUR pin description. Section 1, Added note regarding PUR pin. Table 1-1, Changed SYSRSTIV interrupt event with value 1Ch to Reserved. Section 1, Added note regarding interaction between minimum VCC and SVSH. Section 1, Changed tSENSOR(sample) MIN to 100 µs, and changed note (2). |
SLAS590H February 2012 |
Corrected lost and corrupted symbols throughout. Affected symbols include: Δ θ Ω → ≥ ≤ ≠ Changed ACLK signal description in Section 1. Changed note on Section 1. Changed notes regarding UCA0CLK and UCB0CLK function on Table 1-1 and Table 1-1. |
SLAS590G November 2011 |
Changed limits for wake-up time, LPM3/4 current, reference current, ADC12 maximum frequency, ADC linearity — see the following tables: Changed notes regarding crystal capacitance in Section 1 |
SLAS590F November 2011 |
Corrected terminal assignments for YFF package in Section 1 and Section 1 |
SLAS590E April 2011 |
Updated YFF and ZQE pinout drawings. Changed Tstg maximum to 150°C in Section 1. Changed fXT2,HF,SW MIN to 0.7 MHz in Section 1. |
SLAS590D April 2010 | Production data release |
SLAS590C January 2010 | Changes throughout for updated preview |
SLAS590B July 2009 | Changes throughout for updated preview |
SLAS590A May 2009 | Changes throughout for XMS430F5529 sampling |
SLAS590 September 2008 | Limited product preview release |
Changes from Revision () to Revision ()
Table 6-1 summarizes the available family members.
DEVICE(1)(2) | FLASH (KB) |
SRAM (KB)(5) |
Timer_A(3) | Timer_B(4) | USCI_A: UART, IrDA, SPI |
USCI_B: SPI, I2C |
ADC12_A (channels) |
COMP_B (channels) |
I/Os | PACKAGE |
---|---|---|---|---|---|---|---|---|---|---|
MSP430F5529 | 128 | 8 + 2 | 5, 3, 3 | 7 | 2 | 2 | 14 ext, 2 int | 12 | 63 | 80 PN |
MSP430F5528 | 128 | 8 + 2 | 5, 3, 3 | 7 | 2 | 2 | 10 ext, 2 int | 8 | 47 | 64 RGC, 64 YFF, 80 ZXH, 80 ZQE |
MSP430F5527 | 96 | 6 + 2 | 5, 3, 3 | 7 | 2 | 2 | 14 ext, 2 int | 12 | 63 | 80 PN |
MSP430F5526 | 96 | 6 + 2 | 5, 3, 3 | 7 | 2 | 2 | 10 ext, 2 int | 8 | 47 | 64 RGC, 80 ZXH, 80 ZQE |
MSP430F5525 | 64 | 4 + 2 | 5, 3, 3 | 7 | 2 | 2 | 14 ext, 2 int | 12 | 63 | 80 PN |
MSP430F5524 | 64 | 4 + 2 | 5, 3, 3 | 7 | 2 | 2 | 10 ext, 2 int | 8 | 47 | 64 RGC, 80 ZXH, 80 ZQE |
MSP430F5522 | 32 | 8 + 2 | 5, 3, 3 | 7 | 2 | 2 | 10 ext, 2 int | 8 | 47 | 64 RGC, 80 ZXH, 80 ZQE |
MSP430F5521 | 32 | 6 + 2 | 5, 3, 3 | 7 | 2 | 2 | 14 ext, 2 int | 12 | 63 | 80 PN |
MSP430F5519 | 128 | 8 + 2 | 5, 3, 3 | 7 | 2 | 2 | – | 12 | 63 | 80 PN |
MSP430F5517 | 96 | 6 + 2 | 5, 3, 3 | 7 | 2 | 2 | – | 12 | 63 | 80 PN |
MSP430F5515 | 64 | 4 + 2 | 5, 3, 3 | 7 | 2 | 2 | – | 12 | 63 | 80 PN |
MSP430F5514 | 64 | 4 + 2 | 5, 3, 3 | 7 | 2 | 2 | – | 8 | 47 | 64 RGC, 80 ZXH, 80 ZQE |
MSP430F5513 | 32 | 4 + 2 | 5, 3, 3 | 7 | 2 | 2 | – | 8 | 47 | 64 RGC, 80 ZXH, 80 ZQE |
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing & measurement MCUs
One platform. One ecosystem. Endless possibilities.
Companion products for MSP430F5529
Review products that are frequently purchased or used with this product.
Reference designs for MSP430F5529
Find reference designs leveraging the best in TI technology to solve your system-level challenges.
Figure 7-1 shows the pinout for the MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 devices in the 80-pin PN package.
Figure 7-2 shows the pinout for the MSP430F5528, MSP430F5526, MSP430F5524, and MSP430F5522 devices in the 64-pin RGC package.
Figure 7-3 shows the pinout for the MSP430F5519, MSP430F5517, and MSP430F5515 devices in the 80-pin PN package.
Figure 7-4 shows the pinout for the MSP430F5514 and MSP430F5513 devices in the 64-pin RGC package.
Figure 7-5 shows the pinout for the MSP430F5528, MSP430F5526, MSP430F5524, MSP430F5522, MSP430F5514, and MSP430F5513 devices in the 80-pin ZXH or ZQE package.
Figure 7-6 shows the pinout for the MSP430F5528 device in the 64-pin YFF package. For package dimensions, see the Mechanical Data in Section 11.
Table 7-1 describes the signals for all device and package options.
TERMINAL | I/O(1) | DESCRIPTION | ||||
---|---|---|---|---|---|---|
NAME | NO. | |||||
PN | RGC | YFF | ZXH, ZQE | |||
P6.4/CB4/A4 | 1 | 5 | B2 | C1 | I/O | General-purpose digital I/O |
Comparator_B input CB4 | ||||||
Analog input A4 for ADC (not available on F551x devices) | ||||||
P6.5/CB5/A5 | 2 | 6 | B3 | D2 | I/O | General-purpose digital I/O |
Comparator_B input CB5 | ||||||
Analog input A5 for ADC (not available on F551x devices) | ||||||
P6.6/CB6/A6 | 3 | 7 | A2 | D1 | I/O | General-purpose digital I/O |
Comparator_B input CB6 | ||||||
Analog input A6 for ADC (not available on F551x devices) | ||||||
P6.7/CB7/A7 | 4 | 8 | C5 | D3 | I/O | General-purpose digital I/O |
Comparator_B input CB7 | ||||||
Analog input A7 for ADC (not available on F551x devices) | ||||||
P7.0/CB8/A12 | 5 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
Comparator_B input CB8 (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
Analog input A12 for ADC (not available on F551x devices) | ||||||
P7.1/CB9/A13 | 6 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
Comparator_B input CB9 (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
Analog input A13 for ADC (not available on F551x devices) | ||||||
P7.2/CB10/A14 | 7 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
Comparator_B input CB10 (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
Analog input A14 for ADC (not available on F551x devices) | ||||||
P7.3/CB11/A15 | 8 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
Comparator_B input CB11 (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
Analog input A15 for ADC (not available on F551x devices) | ||||||
P5.0/A8/VREF+/VeREF+ | 9 | 9 | B4 | E1 | I/O | General-purpose digital I/O |
Output of reference voltage to the ADC (not available on F551x devices) | ||||||
Input for an external reference voltage to the ADC (not available on F551x devices) | ||||||
Analog input A8 for ADC (not available on F551x devices) | ||||||
P5.1/A9/VREF-/VeREF- | 10 | 10 | B5 | E2 | I/O | General-purpose digital I/O |
Negative terminal for the ADC reference voltage for both sources, the internal reference voltage, or an external applied reference voltage (not available on F551x devices) | ||||||
Analog input A9 for ADC (not available on F551x devices) | ||||||
AVCC1 | 11 | 11 | A3 | F2 | Analog power supply | |
P5.4/XIN | 12 | 12 | A5 | F1 | I/O | General-purpose digital I/O |
Input terminal for crystal oscillator XT1 | ||||||
P5.5/XOUT | 13 | 13 | A6 | G1 | I/O | General-purpose digital I/O |
Output terminal of crystal oscillator XT1 | ||||||
AVSS1 | 14 | 14 | A4 | G2 | Analog ground supply | |
P8.0 | 15 | N/A | N/A | N/A | I/O | General-purpose digital I/O |
P8.1 | 16 | N/A | N/A | N/A | I/O | General-purpose digital I/O |
P8.2 | 17 | N/A | N/A | N/A | I/O | General-purpose digital I/O |
DVCC1 | 18 | 15 | A7 | H1 | Digital power supply | |
DVSS1 | 19 | 16 | A8 | J1 | Digital ground supply | |
VCORE(3) | 20 | 17 | B8 | J2 | Regulated core power supply output (internal use only, no external current loading) | |
P1.0/TA0CLK/ACLK | 21 | 18 | B7 | H2 | I/O | General-purpose digital I/O with port interrupt |
TA0 clock signal TA0CLK input | ||||||
ACLK output (divided by 1, 2, 4, 8, 16, or 32) | ||||||
P1.1/TA0.0 | 22 | 19 | B6 | H3 | I/O | General-purpose digital I/O with port interrupt |
TA0 CCR0 capture: CCI0A input, compare: Out0 output | ||||||
BSL transmit output | ||||||
P1.2/TA0.1 | 23 | 20 | C6 | J3 | I/O | General-purpose digital I/O with port interrupt |
TA0 CCR1 capture: CCI1A input, compare: Out1 output | ||||||
BSL receive input | ||||||
P1.3/TA0.2 | 24 | 21 | C8 | G4 | I/O | General-purpose digital I/O with port interrupt |
TA0 CCR2 capture: CCI2A input, compare: Out2 output | ||||||
P1.4/TA0.3 | 25 | 22 | C7 | H4 | I/O | General-purpose digital I/O with port interrupt |
TA0 CCR3 capture: CCI3A input compare: Out3 output | ||||||
P1.5/TA0.4 | 26 | 23 | D6 | J4 | I/O | General-purpose digital I/O with port interrupt |
TA0 CCR4 capture: CCI4A input, compare: Out4 output | ||||||
P1.6/TA1CLK/CBOUT | 27 | 24 | D7 | G5 | I/O | General-purpose digital I/O with port interrupt |
TA1 clock signal TA1CLK input | ||||||
Comparator_B output | ||||||
P1.7/TA1.0 | 28 | 25 | D8 | H5 | I/O | General-purpose digital I/O with port interrupt |
TA1 CCR0 capture: CCI0A input, compare: Out0 output | ||||||
P2.0/TA1.1 | 29 | 26 | E5 | J5 | I/O | General-purpose digital I/O with port interrupt |
TA1 CCR1 capture: CCI1A input, compare: Out1 output | ||||||
P2.1/TA1.2 | 30 | 27 | E8 | G6 | I/O | General-purpose digital I/O with port interrupt |
TA1 CCR2 capture: CCI2A input, compare: Out2 output | ||||||
P2.2/TA2CLK/SMCLK | 31 | 28 | E7 | J6 | I/O | General-purpose digital I/O with port interrupt |
TA2 clock signal TA2CLK input | ||||||
SMCLK output | ||||||
P2.3/TA2.0 | 32 | 29 | E6 | H6 | I/O | General-purpose digital I/O with port interrupt |
TA2 CCR0 capture: CCI0A input, compare: Out0 output | ||||||
P2.4/TA2.1 | 33 | 30 | F8 | J7 | I/O | General-purpose digital I/O with port interrupt |
TA2 CCR1 capture: CCI1A input, compare: Out1 output | ||||||
P2.5/TA2.2 | 34 | 31 | F7 | J8 | I/O | General-purpose digital I/O with port interrupt |
TA2 CCR2 capture: CCI2A input, compare: Out2 output | ||||||
P2.6/RTCCLK/DMAE0 | 35 | 32 | F6 | J9 | I/O | General-purpose digital I/O with port interrupt |
RTC clock output for calibration | ||||||
DMA external trigger input | ||||||
P2.7/UCB0STE/UCA0CLK | 36 | 33 | H8 | H7 | I/O | General-purpose digital I/O with port interrupt |
Slave transmit enable – USCI_B0 SPI mode | ||||||
Clock signal input – USCI_A0 SPI slave mode | ||||||
Clock signal output – USCI_A0 SPI master mode | ||||||
P3.0/UCB0SIMO/ UCB0SDA | 37 | 34 | G8 | H8 | I/O | General-purpose digital I/O |
Slave in, master out – USCI_B0 SPI mode | ||||||
I2C data – USCI_B0 I2C mode | ||||||
P3.1/UCB0SOMI/ UCB0SCL | 38 | 35 | H7 | H9 | I/O | General-purpose digital I/O |
Slave out, master in – USCI_B0 SPI mode | ||||||
I2C clock – USCI_B0 I2C mode | ||||||
P3.2/UCB0CLK/UCA0STE | 39 | 36 | G7 | G8 | I/O | General-purpose digital I/O |
Clock signal input – USCI_B0 SPI slave mode | ||||||
Clock signal output – USCI_B0 SPI master mode | ||||||
Slave transmit enable – USCI_A0 SPI mode | ||||||
P3.3/UCA0TXD/ UCA0SIMO | 40 | 37 | G6 | G9 | I/O | General-purpose digital I/O |
Transmit data – USCI_A0 UART mode | ||||||
Slave in, master out – USCI_A0 SPI mode | ||||||
P3.4/UCA0RXD/ UCA0SOMI | 41 | 38 | G5 | G7 | I/O | General-purpose digital I/O |
Receive data – USCI_A0 UART mode | ||||||
Slave out, master in – USCI_A0 SPI mode | ||||||
P3.5/TB0.5 | 42 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
TB0 CCR5 capture: CCI5A input, compare: Out5 output | ||||||
P3.6/TB0.6 | 43 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
TB0 CCR6 capture: CCI6A input, compare: Out6 output | ||||||
P3.7/TB0OUTH/SVMOUT | 44 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
Switch all PWM outputs high impedance input – TB0 (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
SVM output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
P4.0/PM_UCB1STE/ PM_UCA1CLK | 45 | 41 | F5 | E8 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function |
Default mapping: Slave transmit enable – USCI_B1 SPI mode | ||||||
Default mapping: Clock signal input – USCI_A1 SPI slave mode | ||||||
Default mapping: Clock signal output – USCI_A1 SPI master mode | ||||||
P4.1/PM_UCB1SIMO/ PM_UCB1SDA | 46 | 42 | H4 | E7 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function |
Default mapping: Slave in, master out – USCI_B1 SPI mode | ||||||
Default mapping: I2C data – USCI_B1 I2C mode | ||||||
P4.2/PM_UCB1SOMI/ PM_UCB1SCL | 47 | 43 | G4 | D9 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function |
Default mapping: Slave out, master in – USCI_B1 SPI mode | ||||||
Default mapping: I2C clock – USCI_B1 I2C mode | ||||||
P4.3/PM_UCB1CLK/ PM_UCA1STE | 48 | 44 | F4 | D8 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function |
Default mapping: Clock signal input – USCI_B1 SPI slave mode | ||||||
Default mapping: Clock signal output – USCI_B1 SPI master mode | ||||||
Default mapping: Slave transmit enable – USCI_A1 SPI mode | ||||||
DVSS2 | 49 | 39 | H6 | F9 | Digital ground supply | |
DVCC2 | 50 | 40 | H5 | E9 | Digital power supply | |
P4.4/PM_UCA1TXD/ PM_UCA1SIMO | 51 | 45 | H3 | D7 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function |
Default mapping: Transmit data – USCI_A1 UART mode | ||||||
Default mapping: Slave in, master out – USCI_A1 SPI mode | ||||||
P4.5/PM_UCA1RXD/ PM_UCA1SOMI | 52 | 46 | G3 | C9 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function |
Default mapping: Receive data – USCI_A1 UART mode | ||||||
Default mapping: Slave out, master in – USCI_A1 SPI mode | ||||||
P4.6/PM_NONE | 53 | 47 | F3 | C8 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function |
Default mapping: no secondary function. | ||||||
P4.7/PM_NONE | 54 | 48 | E4 | C7 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function |
Default mapping: no secondary function. | ||||||
P5.6/TB0.0 | 55 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
P5.7/TB0.1 | 56 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
P7.4/TB0.2 | 57 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
P7.5/TB0.3 | 58 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
P7.6/TB0.4 | 59 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
P7.7/TB0CLK/MCLK | 60 | N/A | N/A | N/A | I/O | General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) |
TB0 clock signal TBCLK input (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
MCLK output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) | ||||||
VSSU | 61 | 49 | H2 | B8, B9 | USB PHY ground supply | |
PU.0/DP | 62 | 50 | H1 | A9 | I/O | General-purpose digital I/O. Controlled by USB control register |
USB data terminal DP | ||||||
PUR | 63 | 51 | G2 | B7 | I/O | USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to invoke the default USB BSL. Recommended 1-MΩ resistor to ground. See Section 9.5.1 for more information. |
PU.1/DM | 64 | 52 | G1 | A8 | I/O | General-purpose digital I/O. Controlled by USB control register |
USB data terminal DM | ||||||
VBUS | 65 | 53 | F2 | A7 | USB LDO input (connect to USB power source) | |
VUSB | 66 | 54 | F1 | A6 | USB LDO output | |
V18 | 67 | 55 | E2 | B6 | USB regulated power (internal use only, no external current loading) | |
AVSS2 | 68 | 56 | D2 | A5 | Analog ground supply | |
P5.2/XT2IN | 69 | 57 | E1 | B5 | I/O | General-purpose digital I/O |
Input terminal for crystal oscillator XT2 | ||||||
P5.3/XT2OUT | 70 | 58 | D1 | B4 | I/O | General-purpose digital I/O |
Output terminal of crystal oscillator XT2 | ||||||
TEST/SBWTCK(4) | 71 | 59 | E3 | A4 | I | Test mode pin – selects 4-wire JTAG operation |
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated | ||||||
PJ.0/TDO(5) | 72 | 60 | D3 | C5 | I/O | General-purpose digital I/O |
JTAG test data output port | ||||||
PJ.1/TDI/TCLK(5) | 73 | 61 | D4 | C4 | I/O | General-purpose digital I/O |
JTAG test data input | ||||||
Test clock input | ||||||
PJ.2/TMS(5) | 74 | 62 | C1 | A3 | I/O | General-purpose digital I/O |
JTAG test mode select | ||||||
PJ.3/TCK(5) | 75 | 63 | C2 | B3 | I/O | General-purpose digital I/O |
JTAG test clock | ||||||
RST/NMI/SBWTDIO(4) | 76 | 64 | D5 | A2 | I/O | Reset input, active low(6) |
Nonmaskable interrupt input | ||||||
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated | ||||||
P6.0/CB0/A0 | 77 | 1 | B1 | A1 | I/O | General-purpose digital I/O |
Comparator_B input CB0 | ||||||
Analog input A0 for ADC (not available on F551x devices) | ||||||
P6.1/CB1/A1 | 78 | 2 | C3 | B2 | I/O | General-purpose digital I/O |
Comparator_B input CB1 | ||||||
Analog input A1 for ADC (not available on F551x devices) | ||||||
P6.2/CB2/A2 | 79 | 3 | A1 | B1 | I/O | General-purpose digital I/O |
Comparator_B input CB2 | ||||||
Analog input A2 for ADC (not available on F551x devices) | ||||||
P6.3/CB3/A3 | 80 | 4 | C4 | C2 | I/O | General-purpose digital I/O |
Comparator_B input CB3 | ||||||
Analog input A3 for ADC (not available on F551x devices) | ||||||
Reserved | N/A | N/A | N/A | (2) | Reserved. Connect to ground. | |
QFN Pad | N/A | Pad | N/A | N/A | QFN package pad. TI recommends connecting to VSS. |
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
MIN | MAX | UNIT | |
---|---|---|---|
Voltage applied at VCC to VSS | –0.3 | 4.1 | V |
Voltage applied to any pin (excluding VCORE, VBUS, V18)(2) | –0.3 | VCC + 0.3 | V |
Diode current at any device pin | ±2 | mA | |
Maximum operating junction temperature, TJ | 95 | °C | |
Storage temperature, Tstg(3) | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±250 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage during program execution and flash programming (AVCC = DVCC1 = DVCC2 = DVCC)(1)(2) | PMMCOREVx = 0 | 1.8 | 3.6 | V | |
PMMCOREVx = 0, 1 | 2.0 | 3.6 | ||||
PMMCOREVx = 0, 1, 2 | 2.2 | 3.6 | ||||
PMMCOREVx = 0, 1, 2, 3 | 2.4 | 3.6 | ||||
VCC, USB | Supply voltage during USB operation, USB PLL disabled, USB_EN = 1, UPLLEN = 0 |
PMMCOREVx = 0 | 1.8 | 3.6 | V | |
PMMCOREVx = 0, 1 | 2.0 | 3.6 | ||||
PMMCOREVx = 0, 1, 2 | 2.2 | 3.6 | ||||
PMMCOREVx = 0, 1, 2, 3 | 2.4 | 3.6 | ||||
Supply voltage during USB operation, USB PLL enabled(3), USB_EN = 1, UPLLEN = 1 |
PMMCOREVx = 2 | 2.2 | 3.6 | |||
PMMCOREVx = 2, 3 | 2.4 | 3.6 | ||||
VSS | Supply voltage (AVSS = DVSS1 = DVSS2 = DVSS) | 0 | V | |||
TA | Operating free-air temperature | I version | –40 | 85 | °C | |
TJ | Operating junction temperature | I version | –40 | 85 | °C | |
CVCORE | Recommended capacitor at VCORE(4) | 470 | nF | |||
CDVCC/ CVCORE | Capacitor ratio of DVCC to VCORE | 10 | ratio | |||
fSYSTEM | Processor frequency (maximum MCLK frequency)(5) (see Figure 8-1) | PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V (default condition) |
0 | 8.0 | MHz | |
PMMCOREVx = 1, 2.0 V ≤ VCC ≤ 3.6 V |
0 | 12.0 | ||||
PMMCOREVx = 2, 2.2 V ≤ VCC ≤ 3.6 V |
0 | 20.0 | ||||
PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V |
0 | 25.0 | ||||
fSYSTEM_USB | Minimum processor frequency for USB operation | 1.5 | MHz | |||
USB_wait | Wait state cycles during USB operation | 16 | cycles |
PARAMETER | EXECUTION MEMORY | VCC | PMMCOREVx | FREQUENCY (fDCO = fMCLK = fSMCLK) | UNIT | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 MHz | 8 MHz | 12 MHz | 20 MHz | 25 MHz | ||||||||||
TYP | MAX | TYP | MAX | TYP | MAX | TYP | MAX | TYP | MAX | |||||
IAM, Flash | Flash | 3.0 V | 0 | 0.36 | 0.47 | 2.32 | 2.60 | mA | ||||||
1 | 0.40 | 2.65 | 4.0 | 4.4 | ||||||||||
2 | 0.44 | 2.90 | 4.3 | 7.1 | 7.7 | |||||||||
3 | 0.46 | 3.10 | 4.6 | 7.6 | 10.1 | 11.0 | ||||||||
IAM, RAM | RAM | 3.0 V | 0 | 0.20 | 0.24 | 1.20 | 1.30 | mA | ||||||
1 | 0.22 | 1.35 | 2.0 | 2.2 | ||||||||||
2 | 0.24 | 1.50 | 2.2 | 3.7 | 4.2 | |||||||||
3 | 0.26 | 1.60 | 2.4 | 3.9 | 5.3 | 6.2 |
PARAMETER | VCC | PMMCOREVx | –40°C | 25°C | 60°C | 85°C | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
TYP | MAX | TYP | MAX | TYP | MAX | TYP | MAX | |||||
ILPM0,1MHz | Low-power mode 0(3)(4) | 2.2 V | 0 | 73 | 77 | 85 | 80 | 85 | 97 | µA | ||
3.0 V | 3 | 79 | 83 | 92 | 88 | 95 | 105 | |||||
ILPM2 | Low-power mode 2(5)(4) | 2.2 V | 0 | 6.5 | 6.5 | 12 | 10 | 11 | 17 | µA | ||
3.0 V | 3 | 7.0 | 7.0 | 13 | 11 | 12 | 18 | |||||
ILPM3,XT1LF | Low-power mode 3, crystal mode(6)(4) | 2.2 V | 0 | 1.60 | 1.90 | 2.6 | 5.6 | µA | ||||
1 | 1.65 | 2.00 | 2.7 | 5.9 | ||||||||
2 | 1.75 | 2.15 | 2.9 | 6.1 | ||||||||
3.0 V | 0 | 1.8 | 2.1 | 2.9 | 2.8 | 5.8 | 8.3 | |||||
1 | 1.9 | 2.3 | 2.9 | 6.1 | ||||||||
2 | 2.0 | 2.4 | 3.0 | 6.3 | ||||||||
3 | 2.0 | 2.5 | 3.9 | 3.1 | 6.4 | 9.3 | ||||||
ILPM3,VLO | Low-power mode 3, VLO mode(7)(4) | 3.0 V | 0 | 1.1 | 1.4 | 2.7 | 1.9 | 4.9 | 7.4 | µA | ||
1 | 1.1 | 1.4 | 2.0 | 5.2 | ||||||||
2 | 1.2 | 1.5 | 2.1 | 5.3 | ||||||||
3 | 1.3 | 1.6 | 3.0 | 2.2 | 5.4 | 8.5 | ||||||
ILPM4 | Low-power mode 4(8)(4) | 3.0 V | 0 | 0.9 | 1.1 | 1.5 | 1.8 | 4.8 | 7.3 | µA | ||
1 | 1.1 | 1.2 | 2.0 | 5.1 | ||||||||
2 | 1.2 | 1.2 | 2.1 | 5.2 | ||||||||
3 | 1.3 | 1.3 | 1.6 | 2.2 | 5.3 | 8.1 | ||||||
ILPM4.5 | Low-power mode 4.5(9) | 3.0 V | — | 0.15 | 0.18 | 0.35 | 0.26 | 0.5 | 1.0 | µA |
THERMAL METRIC(1) | VALUE | UNIT | |||
---|---|---|---|---|---|
RθJA | Junction-to-ambient thermal resistance, still air | Low-K board (JESD51-3) | LQFP (PN) | 70 | °C/W |
VQFN (RGC) | 55 | ||||
BGA (ZQE) | 84 | ||||
High-K board (JESD51-7) | LQFP (PN) | 45 | |||
VQFN (RGC) | 25 | ||||
BGA (ZQE) | 46 | ||||
RθJC | Junction-to-case thermal resistance | LQFP (PN) | 12 | °C/W | |
VQFN (RGC) | 12 | ||||
BGA (ZQE) | 30 | ||||
RθJB | Junction-to-board thermal resistance | LQFP (PN) | 22 | °C/W | |
VQFN (RGC) | 6 | ||||
BGA (ZQE) | 20 |
PARAMETER(1) | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VIT+ | Positive-going input threshold voltage | 1.8 V | 0.80 | 1.40 | V | ||
3 V | 1.50 | 2.10 | |||||
VIT– | Negative-going input threshold voltage | 1.8 V | 0.45 | 1.00 | V | ||
3 V | 0.75 | 1.65 | |||||
Vhys | Input voltage hysteresis (VIT+ – VIT–) | 1.8 V | 0.3 | 0.85 | V | ||
3 V | 0.4 | 1.0 | |||||
RPull | Pullup and pulldown resistor(2) | For pullup: VIN = VSS For pulldown: VIN = VCC | 20 | 35 | 50 | kΩ | |
CI | Input capacitance | VIN = VSS or VCC | 5 | pF |
PARAMETER(1) | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
t(int) | External interrupt timing(2) | External trigger pulse duration to set interrupt flag | 2.2 V, 3 V | 20 | ns |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
Ilkg(Px.y) | High-impedance leakage current | See (1) (2) | 1.8 V, 3 V | –50 | 50 | nA |