The OPA2171-EP is a 36-V, single-supply, low-noise operational amplifier with the ability to operate on supplies ranging from 2.7 V (±1.35 V) to 36 V (±18 V). These devices are available in micro-packages and offer low offset, drift, and bandwidth with low quiescent current. The single, dual, and quad versions all have identical specifications for maximum design flexibility.
Unlike most operational amplifiers, which are specified at only one supply voltage, the OPA2171-EP is specified from 2.7 to 36 V. Input signals beyond the supply rails do not cause phase reversal. The OPA2171-EP is stable with capacitive loads up to 300 pF. The input can operate 100 mV below the negative rail and within 2 V of the top rail during normal operation. Note that these devices can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail.
The OPA2171-EP operational amplifier is specified from –55°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
OPA2171-EP | VSSOP (8) | 2.30 mm × 2.00 mm |
DATE | REVISION | NOTES |
---|---|---|
September 2015 | * | Initial release. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
+IN A | 3 | I | Noninverting input, channel A |
+IN B | 5 | I | Noninverting input, channel B |
–IN A | 2 | I | Inverting input, channel A |
–IN B | 6 | I | Inverting input, channel B |
OUT A | 1 | O | Output, channel A |
OUT B | 7 | O | Output, channel B |
V+ | 7 | — | Positive (highest) power supply |
V– | 4 | — | Negative (lowest) power supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | ±20 | V | ||
Signal input pins | Voltage | (V–) – 0.5 | (V+) + 0.5 | V |
Current | –10 | 10 | mA | |
Output short circuit(2) | Continuous | |||
Junction temperature | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Supply voltage (V+ – V–) | 4.5 (±2.25) | 36 (±18) | V | ||
Operating temperature, TJ | –55 | 125 | °C |
THERMAL METRIC(1) | OPA2171-EP | UNIT | |
---|---|---|---|
DCU (VSSOP) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 175.2 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 74.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 22.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 22.8 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | |||||||
Input offset voltage | VOS | 0.25 | ±1.8 | mV | |||
Over temperature | TJ = –55°C to 125°C | 0.3 | ±2 | mV | |||
Drift | dVOS/dT | TJ = –55°C to 125°C | 0.3 | µV/°C | |||
vs power supply | PSRR | VS = 4 to 36 V, TA = –55°C to 125°C | 1 | ±5 | µV/V | ||
Channel separation, dc | dc | 5 | µV/V | ||||
INPUT BIAS CURRENT | |||||||
Input bias current | IB | ±8 | ±15 | pA | |||
Over temperature | TJ = –55°C to 125°C | ±4 | nA | ||||
Input offset current | IOS | ±4 | pA | ||||
Over temperature | TJ = –55°C to 125°C | ±4 | nA | ||||
NOISE | |||||||
Input voltage noise | ƒ = 0.1 to 10 Hz | 3 | µVPP | ||||
Input voltage noise density | en | ƒ = 100 Hz | 25 | nV/√Hz | |||
ƒ = 1 kHz | 14 | nV/√Hz | |||||
INPUT VOLTAGE | |||||||
Common-mode voltage range(1) | VCM | (V–) – 0.1 V | (V+) – 2 V | V | |||
Common-mode rejection ratio | CMRR | VS = ±2 V, (V–) – 0.1 V < VCM < (V+) – 2 V, TJ = –55°C to 125°C |
87 | 104 | dB | ||
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V, TJ = –55°C to 125°C |
104 | 120 | dB | ||||
INPUT IMPEDANCE | |||||||
Differential | 100 || 3 | MΩ || pF | |||||
Common-mode | 6 || 3 | 1012Ω || pF | |||||
OPEN-LOOP GAIN | |||||||
Open-loop voltage gain | AOL | VS = 4 to 36 V, (V–) + 0.35 V < VO < (V+) – 0.35 V, TJ = –55°C to 125°C | 110 | 130 | dB | ||
FREQUENCY RESPONSE | |||||||
Gain bandwidth product | GBP | 3.0 | MHz | ||||
Slew rate | SR | G = +1 | 1.5 | V/µs | |||
Settling time | tS | To 0.1%, VS = ±18 V, G = +1, 10-V step | 6 | µs | |||
To 0.01% (12 bit), VS = ±18 V, G = +1, 10-V step | 10 | µs | |||||
Overload recovery time | VIN × Gain > VS | 2 | µs | ||||
Total harmonic distortion + noise | THD+N | G = +1, ƒ = 1kHz, VO = 3VRMS | 0.0002% | ||||
OUTPUT | |||||||
Voltage output swing from rail | VO | VS = 5 V, RL = 10 kΩ | 30 | mV | |||
Over temperature | RL = 10 kΩ, AOL ≥ 110 dB, TJ = –55°C to 125°C |
(V–) + 0.35 | (V+) – 0.35 | V | |||
Short-circuit current | ISC | +25/–35 | mA | ||||
Capacitive load drive | CLOAD | See Typical Characteristics | pF | ||||
Open-loop output resistance | RO | ƒ = 1 MHz, IO = 0 A | 150 | Ω | |||
POWER SUPPLY | |||||||
Specified voltage range | VS | 2.7 | 36 | V | |||
Quiescent current per amplifier | IQ | IO = 0 A | 475 | 595 | µA | ||
Over temperature | IO = 0 A, TJ = –55°C to 125°C | 650 | µA | ||||
TEMPERATURE | |||||||
Operating temperature | TJ | –55 | 125 | °C |
DESCRIPTION | FIGURE |
---|---|
Offset Voltage Production Distribution | Figure 1 |
Offset Voltage Drift Distribution | Figure 2 |
Offset Voltage vs Temperature | Figure 3 |
Offset Voltage vs Common-Mode Voltage | Figure 4 |
Offset Voltage vs Common-Mode Voltage (Upper Stage) | Figure 5 |
Offset Voltage vs Power Supply | Figure 6 |
IB and IOS vs Common-Mode Voltage | Figure 7 |
Input Bias Current vs Temperature | Figure 8 |
Output Voltage Swing vs Output Current (Maximum Supply) | Figure 9 |
CMRR and PSRR vs Frequency (Referred-to Input) | Figure 10 |
CMRR vs Temperature | Figure 11 |
PSRR vs Temperature | Figure 12 |
0.1-Hz to 10-Hz Noise | Figure 13 |
Input Voltage Noise Spectral Density vs Frequency | Figure 14 |
THD+N Ratio vs Frequency | Figure 15 |
THD+N vs Output Amplitude | Figure 16 |
Quiescent Current vs Temperature | Figure 17 |
Quiescent Current vs Supply Voltage | Figure 18 |
Open-Loop Gain and Phase vs Frequency | Figure 19 |
Closed-Loop Gain vs Frequency | Figure 20 |
Open-Loop Gain vs Temperature | Figure 21 |
Open-Loop Output Impedance vs Frequency | Figure 22 |
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) | Figure 23, Figure 24 |
No Phase Reversal | Figure 25 |
Positive Overload Recovery | Figure 26 |
Negative Overload Recovery | Figure 27 |
Small-Signal Step Response (100 mV) | Figure 28, Figure 29 |
Large-Signal Step Response | Figure 30, Figure 31 |
Large-Signal Settling Time (10-V Positive Step) | Figure 32 |
Large-Signal Settling Time (10-V Negative Step) | Figure 33 |
Short-Circuit Current vs Temperature | Figure 34 |
Maximum Output Voltage vs Frequency | Figure 35 |
Channel Separation vs Frequency | Figure 36 |
The OPA2171-EP operational amplifier provides high overall performance, making it ideal for many general-purpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the entire temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
The OPA2171-EP amplifier is specified for operation from 2.7 to 36 V (±1.35 to ±18 V). Many of the specifications apply from –55°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in Typical Characteristics.
The OPA2171-EP has an internal phase-reversal protection. Many operational amplifiers exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input of the OPA2171-EP prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. Figure 37 shows this performance.
The input common-mode voltage range of the OPA2171-EP extends 100 mV below the negative rail and within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail. Table 2 summarizes the typical performance in this range.
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Input Common-Mode Voltage | (V+) – 2 | (V+) + 0.1 | V | ||
Offset voltage | 7 | mV | |||
vs Temperature | 12 | µV/°C | |||
Common-mode rejection | 65 | dB | |||
Open-loop gain | 60 | dB | |||
GBW | 0.7 | MHz | |||
Slew rate | 0.7 | V/µs | |||
Noise at ƒ = 1kHz | 30 | nV/√Hz |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Designers often ask about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to 10 mA as stated in Absolute Maximum Ratings. Figure 38 shows how a series input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its value should be kept to a minimum in noise-sensitive applications.
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbed by the protection circuitry is then dissipated as heat.
When the operational amplifier connects into a circuit, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through ESD cells and rarely involves the absorption device.
If there is uncertainty about the ability of the supply to absorb this current, external Zener diodes may be added to the supply pins. Select the Zener voltage such that the diode does not turn on during normal operation.
However, its Zener voltage should be low enough so that the Zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level.
Figure 39 shows a capacitive load drive solution using an isolation resistor. The OPA2171-EP device can be used capacitive loads such as cable shields, reference buffers, MOSFET gates, and diodes. The circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the open loop gain of the system to ensure the circuit has sufficient phase margin.
The design requirements are:
Figure 39 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the circuit in Figure 39. Not shown in Figure 39 is the open-loop output resistance of the op amp, Ro.
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro + RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB/decade. Figure 40 depicts the concept. The 1/β curve for a unity-gain buffer is 0 dB.
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a measurement of overshoot percentage and AC gain peaking of the circuit using a function generator, oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3 shows the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For more details on this design and other alternative devices that can be used in place of the OPA171, refer to the Precision Design, Capacitive Load Drive Solution using an Isolation Resistor (TIPD128).
PHASE MARGIN | OVERSHOOT | AC GAIN PEAKING |
---|---|---|
45° | 23.3% | 2.35 dB |
60° | 8.8% | 0.28 dB |
The dynamic characteristics of the OPA2171-EP have been optimized for commonly encountered operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. Figure 41 and Figure 42 illustrate graphs of small-signal overshoot versus capacitive load for several values of ROUT. Also, refer to Applications Bulletin AB-028 (SBOA015), available for download from www.ti.com for details of analysis techniques and application circuits.
The OPA2171-EP is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For detailed information on bypass capacitor placement, see the Layout section.