The OPAx333 series of CMOS operational amplifiers use a proprietary auto-calibration technique to simultaneously provide very low offset voltage (10 μV, maximum) and near-zero drift over time and temperature. These miniature, high-precision, low quiescent current amplifiers offer high-impedance inputs that have a common-mode range 100 mV beyond the rails, and rail-to-rail output that swings within 50 mV of the rails. Single or dual supplies as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V) can be used. These devices are optimized for low-voltage, single-supply operation.
The OPAx333 family offers excellent CMRR without the crossover associated with traditional complementary input stages. This design results in superior performance for driving analog-to-digital converters (ADCs) without degradation of differential linearity.
The OPA333 (single version) is available in the 5-pin SOT-23, SOT, and 8-pin SOIC packages, while the OPA2333 (dual version) is available in the 8-pin VSON, SOIC, and VSSOP packages. All versions are specified for operation from –40°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
OPA333 | SOT-23 (5) | 2.90 mm × 1.60 mm |
SOT (5) | 2.00 mm x 1.25 mm | |
SOIC (8) | 4.90 mm × 3.90 mm | |
OPA2333 | VSON (8) | 3.00 mm × 3.00 mm |
SOIC (8) | 4.90 mm × 3.90 mm | |
VSSOP (8) | 3.00 mm × 3.00 mm |
Changes from D Revision (November 2013) to E Revision
Changes from C Revision (May 2007) to D Revision
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | SOIC | SOT | SC70 | ||
+IN | 3 | 3 | 1 | I | Noninverting input |
–IN | 2 | 4 | 3 | I | Inverting input |
NC | 1, 5, 8 | — | — | — | No internal connection (can be left floating) |
OUT | 6 | 1 | 4 | O | Output |
V+ | 7 | 5 | 5 | — | Positive (highest) power supply |
V– | 4 | 2 | 2 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | VSON | SOIC, VSSOP | ||
+IN | — | — | I | Noninverting input |
+IN A | 3 | 3 | I | Noninverting input, channel A |
+IN B | 5 | 5 | I | Noninverting input, channel B |
–IN | — | — | I | Inverting input |
–IN A | 2 | 2 | I | Inverting input, channel A |
–IN B | 6 | 6 | I | Inverting input, channel B |
OUT | — | — | O | Output |
OUT A | 1 | 1 | O | Output, channel A |
OUT B | 7 | 7 | O | Output, channel B |
V+ | 8 | 8 | — | Positive (highest) power supply |
V– | 4 | 4 | — | Negative (lowest) power supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | Supply | 7 | V | |
Signal input terminals(2) | –0.3 | (V+) + 0.3 | ||
Current | Signal input terminals(2) | –1 | 1 | mA |
Output short-circuit(3) | Continuous | |||
Operating junction temperature, TJ | 150 | °C | ||
Operating temperature, TA | –40 | 150 | ||
Storage temperature, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage, VS | 1.8 | 5.5 | V | |
Specified temperature | –40 | 125 | °C |
THERMAL METRIC(1) | OPA333 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | DBV (SOT) | DCK (SC70) | |||
8 PINS | 5 PINS | 5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 140.1 | 220.8 | 298.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 89.8 | 97.5 | 65.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 80.6 | 61.7 | 97.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 28.7 | 7.6 | 0.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 80.1 | 61.1 | 95.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | — | °C/W |
THERMAL METRIC(1) | OPA2333 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | DGK (VSSOP) | DRB (VSON) | |||
8 PINS | 8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 124.0 | 180.3 | 46.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 73.7 | 48.1 | 26.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 64.4 | 100.9 | 22.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 18.0 | 2.4 | 1.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 63.9 | 99.3 | 22.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | 10.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
OFFSET VOLTAGE | ||||||
VOS | Input offset voltage | VS = 5 V | 2 | 10 | μV | |
dVOS/dT | Input offset voltage drift | TA = –40°C to 125°C | 0.02 | 0.05 | μV/°C | |
PSRR | Power-supply rejection ratio | VS = 1.8 V to 5.5 V, TA = –40°C to 125°C | 1 | 5 | μV/V | |
Long-term stability(1) | See note (1) | µV | ||||
Channel separation, dc | 0.1 | μV/V | ||||
INPUT BIAS CURRENT | ||||||
IB | Input bias current | TA= 25°C | ±70 | ±200 | pA | |
TA = –40°C to 125°C | ±150 | |||||
IOS | Input offset current | ±140 | ±400 | |||
NOISE | ||||||
Input voltage noise | f = 0.01 Hz to 1 Hz | 0.3 | μVPP | |||
f = 0.1 Hz to 10 Hz | 1.1 | |||||
in | Input current noise | f = 10 Hz | 100 | fA/√Hz | ||
INPUT VOLTAGE | ||||||
VCM | Common-mode voltage range | (V–) – 0.1 | (V+) + 0.1 | V | ||
CMRR | Common-mode rejection ratio | (V–) – 0.1 V < VCM < (V+) + 0.1 V, TA = –40°C to 125°C |
106 | 130 | dB | |
INPUT CAPACITANCE | ||||||
Differential | 2 | pF | ||||
Common-mode | 4 | pF | ||||
OPEN-LOOP GAIN | ||||||
AOL | Open-loop voltage gain | (V–) + 100 mV < VO < (V+) – 100 mV, RL = 10 kΩ, TA = –40°C to 125°C |
106 | 130 | dB | |
FREQUENCY RESPONSE | ||||||
GBW | Gain-bandwidth product | CL = 100 pF | 350 | kHz | ||
SR | Slew rate | G = +1 | 0.16 | V/μs | ||
OUTPUT | ||||||
Voltage output swing from rail | RL = 10 kΩ | 30 | 50 | mV | ||
RL = 10 kΩ, TA = –40°C to 125°C | 70 | |||||
ISC | Short-circuit current | ±5 | mA | |||
CL | Capacitive load drive | See Typical Characteristics | ||||
Open-loop output impedance | f = 350 kHz, IO = 0 A | 2 | kΩ | |||
POWER SUPPLY | ||||||
VS | Specified voltage range | 1.8 | 5.5 | V | ||
IQ | Quiescent current per amplifier | IO = 0 A | 17 | 25 | μA | |
TA = –40°C to 125°C | 28 | |||||
Turn-on time | VS = +5 V | 100 | μs | |||
TEMPERATURE | ||||||
TA | Specified range | –40 | 125 | °C | ||
Operating range | –40 | 150 | °C | |||
Tstg | Storage range | –65 | 150 | °C |
TITLE | FIGURE |
---|---|
Offset Voltage Production Distribution | Figure 1 |
Offset Voltage Drift Production Distribution | Figure 2 |
Open-Loop Gain vs Frequency | Figure 3 |
Common-Mode Rejection Ratio vs Frequency | Figure 4 |
Power-Supply Rejection Ratio vs Frequency | Figure 5 |
Output Voltage Swing vs Output Current | Figure 6 |
Input Bias Current vs Common-Mode Voltage | Figure 7 |
Input Bias Current vs Temperature | Figure 8 |
Quiescent Current vs Temperature | Figure 9 |
Large-Signal Step Response | Figure 10 |
Small-Signal Step Response | Figure 11 |
Positive Overvoltage Recovery | Figure 12 |
Negative Overvoltage Recovery | Figure 13 |
Settling Time vs Closed-Loop Gain | Figure 14 |
Small-Signal Overshoot vs Load Capacitance | Figure 15 |
0.1-Hz to 10-Hz Noise | Figure 16 |
Current and Voltage Noise Spectral Density vs Frequency | Figure 17 |