The OPA350 series of rail-to-rail CMOS operational amplifiers are optimized for low voltage, single-supply operation. Rail-to-rail input and output, low noise (5 nV/√Hz), and high speed operation (38 MHz, 22 V/μs) make the amplifiers ideal for driving sampling Analog-to-Digital (A/D) converters. They are also suited for cell phone PA control loops and video processing (75-Ω drive capability), as well as audio and general purpose applications. Single, dual, and quad versions have identical specifications for maximum design flexibility.
The OPA350 series operates on a single supply as low as 2.5 V, with an input common-mode voltage range that extends 300 mV below ground and 300 mV above the positive supply. Output voltage swing is to within 10 mV of the supply rails, with a 10-kΩ load. Dual and quad designs feature completely independent circuitry for lowest crosstalk and freedom from interaction.
The single (OPA350) and dual (OPA2350) come in the miniature MSOP-8 surface mount, SO-8 surface mount, and DIP-8 packages. The quad (OPA4350) packages are in the space-saving SSOP-16 surface mount and SO-14 surface mount. All are specified from −40°C to 85°C and operate from −55°C to 150°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
OPA350 | MSOP (8) | 3.00 mm × 3.00 mm |
SOIC (8) | 3.91 mm × 4.90 mm | |
PDIP (8) | 6.35 mm × 9.81 mm | |
OPA2350 | MSOP (8) | 3.00 mm × 3.00 mm |
SOIC (8) | 3.91 mm × 4.90 mm | |
PDIP (8) | 6.35 mm × 9.81 mm | |
OPA4350 | SSOP (16) | 3.90 mm × 4.90 mm |
SOIC (14) | 3.91 mm × 8.65 mm |
Changes from C Revision (January 2005) to D Revision
PIN | I/O | DESCRIPTION | ||||
---|---|---|---|---|---|---|
NAME | OPA350 NO. |
OPA2350 NO. |
OPA4350 SO-14 NO. |
OPA4350 SSOP NO. |
||
NC | 1, 5, 8 | — | — | 8, 9 | — | No internal connection |
–In | 2 | — | — | — | I | Inverting input |
+In | 3 | — | — | — | I | Noninverting input |
V– | 4 | 4 | 11 | 13 | I | Negative power supply |
Output | 6 | — | — | — | O | Output |
V+ | 7 | 8 | 4 | 4 | I | Positive power supply |
Out A | — | 1 | 1 | 1 | O | Output channel A |
–In A | — | 2 | 2 | 2 | I | Inverting input channel A |
+In A | — | 3 | 3 | 3 | I | Noninverting input channel A |
+In B | — | 5 | 5 | 5 | I | Noninverting input channel B |
–In B | — | 6 | 6 | 6 | I | Inverting input channel B |
Out B | — | 7 | 7 | 7 | O | Output channel B |
Out C | — | — | 8 | 10 | O | Output channel C |
–In C | — | — | 9 | 11 | I | Inverting input channel C |
+In C | — | — | 10 | 12 | I | Noninverting input channel C |
+In D | — | — | 12 | 14 | I | Noninverting input channel D |
–In D | — | — | 13 | 15 | I | Inverting input channel D |
Out D | — | — | 14 | 16 | O | Output channel D |