The OPA373 and OPA374 families of operational amplifiers are low power and low cost with excellent bandwidth (6.5 MHz) and slew rate (5 V/µs). The input range extends 200 mV beyond the rails and the output range is within 25 mV of the rails. The speed-power ratio and small size make them ideal for portable and battery-powered applications.
The OPA373 family includes a shutdown mode. Under logic control, the amplifiers can be switched from normal operation to a standby current that is less than 1 µA.
The OPA373 and OPA374 families of operational amplifiers are specified for single or dual power supplies of 2.7 V to 5.5 V, with operation from 2.3 V to 5.5 V. All models are specified for –40°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
OPA373 | SOIC (8) | 4.90 mm × 3.91 mm |
SOT-23 (6) | 2.90 mm × 1.60 mm | |
OPA374 | SOIC (8) | 4.90 mm × 3.91 mm |
SOT-23 (5) | 2.90 mm × 1.60 mm | |
OPA2373 | VSON (10) | 3.00 mm × 3.00 mm |
VSSOP (10) | 3.00 mm × 3.00 mm | |
OPA2374 | SOIC (8) | 4.90 mm × 3.91 mm |
SOT-23 (8) | 2.90 mm × 1.63 mm | |
OPA4374 | SOIC (14) | 8.65 mm × 3.91 mm |
TSSOP (14) | 5.00 mm × 4.40 mm |
Changes from E Revision (May 2008) to F Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOIC | SOT-23 | ||
Enable | 8 | 5 | I | Enable |
–IN | 2 | 4 | I | Negative (inverting) input |
+IN | 3 | 3 | I | Positive (noninverting) input |
NC | 1, 5 | — | — | No internal connection (can be left floating) |
OUT | 6 | 1 | O | Output |
V– | 4 | 2 | — | Negative (lowest) power supply |
V+ | 7 | 6 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | VSON | VSSOP | ||
Enable A | 5 | 5 | I | Enable A amplifier |
Enable B | 6 | 6 | I | Enable B amplifier |
–IN A | 2 | 2 | I | Inverting input, channel A |
+IN A | 3 | 3 | I | Noninverting input, channel A |
–IN B | 8 | 8 | I | Inverting input, channel B |
+IN B | 7 | 7 | I | Noninverting input, channel B |
OUT A | 1 | 1 | O | Output, channel A |
OUT B | 9 | 9 | O | Output, channel B |
V– | 4 | 4 | — | Negative (lowest) power supply |
V+ | 10 | 10 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOIC | SOT-23 | ||
–IN | 2 | 4 | I | Negative (inverting) input |
+IN | 3 | 3 | I | Positive (noninverting) input |
NC | 1, 5, 8 | — | — | No internal connection (can be left floating) |
OUT | 6 | 1 | O | Output |
V– | 4 | 2 | — | Negative (lowest) power supply |
V+ | 7 | 5 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOIC | SOT-23 | ||
–IN A | 2 | 2 | I | Inverting input, channel A |
+IN A | 3 | 3 | I | Noninverting input, channel A |
–IN B | 6 | 6 | I | Inverting input, channel B |
+IN B | 5 | 5 | I | Noninverting input, channel B |
OUT A | 1 | 1 | O | Output, channel A |
OUT B | 7 | 7 | O | Output, channel B |
V– | 4 | 4 | — | Negative (lowest) power supply |
V+ | 8 | 8 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOIC | TSSOP | ||
–IN A | 2 | 2 | I | Inverting input, channel A |
+IN A | 3 | 3 | I | Noninverting input, channel A |
–IN B | 6 | 6 | I | Inverting input, channel B |
+IN B | 5 | 5 | I | Noninverting input, channel B |
–IN C | 9 | 9 | I | Inverting input, channel C |
+IN C | 10 | 10 | I | Noninverting input, channel C |
–IN D | 13 | 13 | I | Inverting input, channel D |
+IN D | 12 | 12 | I | Noninverting input, channel D |
OUT A | 1 | 1 | O | Output, channel A |
OUT B | 7 | 7 | O | Output, channel B |
OUT C | 8 | 8 | O | Output, channel C |
OUT D | 14 | 14 | O | Output, channel D |
V– | 11 | 11 | — | Negative (lowest) power supply |
V+ | 4 | 4 | — | Positive (highest) power supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | Supply | 7 | V | |
Signal input pin(2) | −0.5 | (V+) + 0.5 | ||
Current | Signal input pin(2) | –10 | 10 | mA |
Output short-circuit(3) | Continuous | |||
Temperature | Operating, TA | –55 | 150 | °C |
Junction, TJ | 150 | |||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | ±1.35 (2.7) | ±2.75 (5.5) | V | |
TA | Operating temperature | –40 | 125 | °C |
THERMAL METRIC(1) | OPA373 | UNIT | ||
---|---|---|---|---|
D (SOIC) | DBV (SOT-23) | |||
8 PINS | 6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 128.4 | 184.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 76.7 | 146.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 68.8 | 36.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 27.9 | 33.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 68.3 | 35.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
THERMAL METRIC(1) | OPA374 | UNIT | ||
---|---|---|---|---|
D (SOIC) | DBV (SOT-23) | |||
8 PINS | 5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 125.1 | 220.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 71.7 | 129 | °C/W |
RθJB | Junction-to-board thermal resistance | 65.5 | 46.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 26.2 | 21 | °C/W |
ψJB | Junction-to-board characterization parameter | 65 | 45.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
THERMAL METRIC(1) | OPA2373 | UNIT | ||
---|---|---|---|---|
DGS (VSON) | DRC (VSSOP) | |||
10 PINS | 10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 170.6 | 56.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 59.8 | 76.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 91 | 30.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 10.4 | 3.7 | °C/W |
ψJB | Junction-to-board characterization parameter | 89.6 | 30.7 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | 11.4 | °C/W |
THERMAL METRIC(1) | OPA2374 | UNIT | ||
---|---|---|---|---|
D (SOIC) | DCN (SOT-23) | |||
8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 117.8 | 171.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 63.1 | 73.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 58.4 | 106.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 19.3 | 15.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 57.9 | 105.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
THERMAL METRIC(1) | OPA4374 | UNIT | ||
---|---|---|---|---|
D (SOIC) | PW (TSSOP) | |||
14 PINS | 14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 86.5 | 112.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 45 | 34.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 41.1 | 57.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 12.3 | 2.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 40.8 | 56.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | |||||||
VOS | Input offset voltage | VS = 5 V | 1 | 5 | mV | ||
Input offset voltage versus temperature |
TA = –40°C to 125°C | 6.5 | mV | ||||
dVOS/dT | Input offset voltage versus drift |
TA = –40°C to +125°C | 3 | µV/°C | |||
PSRR | Input offset voltage versus power supply |
VS = 2.7 V to 5.5 V, VCM < (V+) – 2 V |
TA = 25°C | 25 | 100 | µV/V | |
TA = –40°C to 125°C | 150 | ||||||
Channel separation, DC | 0.4 | µV/V | |||||
At f = 1 kHz | 128 | dB | |||||
INPUT VOLTAGE | |||||||
VCM | Common-mode voltage range | (V–) – 0.2 | (V+) + 0.2 | V | |||
CMRR | Common-mode rejection ratio | (V–) – 0.2 V < VCM < (V+) – 2 V | TA = 25°C | 80 | 90 | dB | |
TA = –40°C to 125°C | 70 | ||||||
VS = 5.5 V, (V–) – 0.2 V < VCM < (V+) + 0.2 V |
TA = 25°C | 66 | dB | ||||
TA = –40°C to 125°C | 60 | dB | |||||
INPUT BIAS CURRENT | |||||||
IB | Input bias current | ±0.5 | ±10 | pA | |||
IOS | Input offset current | ±0.5 | ±10 | pA | |||
INPUT IMPEDANCE | |||||||
Differential | 1013 || 3 | Ω || pF | |||||
Common-mode | 1013 || 6 | Ω || pF | |||||
NOISE | |||||||
Input voltage noise | VCM < (V+) – 2 V, f = 0.1 Hz to 10 Hz | 10 | µVPP | ||||
en | Input voltage noise density | VCM < (V+) – 2 V, f = 10 kHz | 15 | nV/√Hz | |||
in | Input current noise density | VCM < (V+) – 2 V, f = 10 kHz | 4 | fA/√Hz | |||
OPEN-LOOP GAIN | |||||||
AOL | Open-loop voltage gain | VS = 5 V, RL = 100 kΩ, 0.025 V < VO < 4.975 V |
TA = 25°C | 94 | 110 | dB | |
TA = –40°C to 125°C | 80 | ||||||
VS = 5 V, RL = 5 kΩ, 0.125 V < VO < 4.875 V |
TA = 25°C | 94 | 106 | dB | |||
TA = –40°C to 125°C | 80 | ||||||
OUTPUT | |||||||
Voltage output swing from rail | RL = 100 kΩ | TA = 25°C | 18 | 25 | mV | ||
TA = –40°C to 125°C | 25 | mV | |||||
RL = 5 kΩ | TA = 25°C | 100 | 125 | mV | |||
TA = –40°C to 125°C | 125 | mV | |||||
ISC | Short-circuit current | See Typical Characteristics | |||||
CLOAD | Capacitive load drive | See Typical Characteristics | |||||
RO | Open-loop output impedance | f = 1 MHz, IO = 0 mA | 220 | Ω | |||
FREQUENCY RESPONSE | |||||||
GBW | Gain-bandwidth product | CL = 100 pF | 6.5 | MHz | |||
SR | Slew rate | CL = 100 pF, G = +1 | 5 | V/µs | |||
tS | Settling time | 0.1%, CL = 100 pF, VS = 5 V, 2-V step, G = +1 |
1 | µs | |||
0.01%, CL = 100 pF, VS = 5 V, 2-V step, G = +1 |
1.5 | µs | |||||
Overload recovery time | CL = 100 pF, VIN ● Gain > VS | 0.3 | µs | ||||
THD+N | Total harmonic distortion + noise | CL = 100 pF, VS = 5 V, VO = 3 VPP, G = +1, f = 1 kHz |
0.0013% | ||||
ENABLE OR SHUTDOWN | |||||||
tOFF | Turnoff time | 3 | µs | ||||
tON | Turnon time | 12 | µs | ||||
VL | Logic low threshold | Shutdown | V– | (V–) + 0.8 | V | ||
VH | Logic high threshold | Amplifier is active | (V–) + 2 | V+ | V | ||
Input bias current of Enable pin | 0.2 | µA | |||||
IQ(sd) | Quiescent current at shutdown (per amplifier) |
< 0.5 | 1 | µA | |||
POWER SUPPLY | |||||||
VS | Specified voltage range | 2.7 | 5.5 | V | |||
Operating voltage range | 2.3 to 5.5 | V | |||||
IQ | Quiescent current (per amplifier) |
IO = 0 mA | TA = 25°C | 585 | 750 | µA | |
TA = –40°C to 125°C | 800 | µA | |||||
TEMPERATURE | |||||||
Specified range | –40 | 125 | °C | ||||
TA | Operating range | –55 | 150 | °C | |||
Tstg | Storage range | –65 | 150 | °C |
The OPAx373 and OPAx374 operational amplifiers (op amps) are suitable for a broad range of general-purpose applications. As unity-gain stable devices and outstanding AC performance, these op amps are ideal for audio applications. The class AB output stage is capable of driving 100-kΩ loads connected to any point between V+ and ground. These devices are well-suited for nearly any single-supply application up to a supply voltage of
5.5 V because the input common-mode voltage range includes both rails. Rail-to-rail input and output swing significantly increases the overall device dynamic range, especially in low-supply applications.
The OPA373 and OPA374 op amps are specified and tested over a power-supply range of 2.7 V to 5.5 V
(±1.35 V to ±2.75 V). However, the supply voltage may range from 2.3 V to 5.5 V (±1.15 V to ±2.75 V). Supply voltages higher than 7 V (absolute maximum) can permanently damage the amplifier. Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics.
The input common-mode voltage range of the OPA373 and OPA374 series extends 200 mV beyond the supply rails. This extended range is achieved with a complementary input stage: an N-channel input differential pair in parallel with a P-channel differential pair. The N-channel pair is active for input voltages close to the positive rail, typically (V+) − 1.65 V to 200 mV above the positive supply, while the P-channel pair is on for inputs from
200 mV below the negative supply to approximately (V+) − 1.65 V. There is a 500-mV transition region, typically (V+) − 1.9 V to (V+) − 1.4 V, in which both pairs are on. This 500-mV transition region, shown in Figure 21, can vary ±300 mV with process variation. Thus, the transition region (that is, both stages on) can range from
(V+) − 2.2 V to (V+) − 1.7 V on the low end, up to (V+) − 1.6 V to (V+) − 1.1 V on the high end. Within the
500-mV transition region, PSRR, CMRR, offset voltage, offset drift, and THD may be degraded, compared to device operation outside this region.
The input common-mode range extends from (V−) − 0.2 V to (V+) + 0.2 V. For normal operation, inputs must be limited to this range. The absolute maximum input voltage is 500 mV beyond the supplies. Inputs greater than the input common-mode range but less than the maximum input voltage, while not valid, do not cause any damage to the op amp. Unlike some other op amps, if input current is limited, the inputs may go beyond the supplies without phase inversion, as shown in Figure 22.
Normally, input bias current is approximately 500 fA; however, input voltages exceeding the power supplies by more than 500 mV can cause excessive current to flow in or out of the input pins. Momentary voltages greater than 500 mV beyond the power supply can be tolerated if the current on the input pins is limited to 10 mA. This limiting is easily accomplished with an input resistor; see Figure 23. Many input signals are inherently current-limited to less than 10 mA, therefore, a limiting resistor is not required.
A class AB output stage with common-source transistors is used to achieve rail-to-rail output. For light resistive loads ( > 100 kΩ), the output voltage can typically swing to within 18 mV from the supply rails. With moderate resistive loads (5 kΩ to 50 kΩ), the output can typically swing to within 100 mV from the supply rails and maintain high open-loop gain. See Figure 12 for more information.
The OPA373 series op amps can drive a wide range of capacitive loads. However, under certain conditions, all op amps may become unstable. Op amp configuration, gain, and load value are some of the factors to consider when determining stability. An op amp in unity-gain configuration is the most susceptible to the effects of capacitive load. The capacitive load reacts with the op amp output resistance, along with any additional load resistance, to create a pole in the small-signal response that degrades the phase margin. The OPA373 series op amps perform well in unity-gain configuration, with a pure capacitive load up to approximately 250 pF. Increased gains allow the amplifier to drive more capacitance. See Figure 17 for further details.
One method of improving capacitive load drive in the unity-gain configuration is to insert a small (10-Ω to 20-Ω) resistor, RS, in series with the output, as shown in Figure 24. This configuration significantly reduces ringing while maintaining DC performance for purely capacitive loads. When there is a resistive load in parallel with the capacitive load, RS must be placed within the feedback loop as shown to allow the feedback loop to compensate for the voltage divider created by RS and RL.
In unity-gain inverter configuration, phase margin can be reduced by the reaction between the capacitance at the op amp input and the gain setting resistors, thus degrading capacitive load drive. Best performance is achieved by using small-valued resistors. However, when large-valued resistors cannot be avoided, a small (4-pF to 6-pF) capacitor, CFB, can be inserted in the feedback, as shown in Figure 25. This technique significantly reduces overshoot by compensating the effect of capacitance, CIN, which includes the amplifier input capacitance and printed-circuit board (PCB) parasitic capacitance.
For example, when driving a 100-pF load in unity-gain inverter configuration, adding a 6-pF capacitor in parallel with the 10-kΩ feedback resistor decreases overshoot from 57% to 12%, as shown in Figure 26.
The OPA373 and OPA374 series op amps typically require 585-µA quiescent current. The enable or shutdown feature of the OPA373 allows the op amp to be shut off to reduce this current to less than 1 µA.
The OPAx374 has a single functional mode and is operational when the power-supply voltage is greater than
2.7 V (±1.35 V). The maximum power supply voltage for the OPAx374 is 5.5 V (±2.75 V).
The OPAx373 has two functional modes: active and shutdown. When the voltage at the Enable pin is from V– to (V–) + 0.8 V, the device is in shutdown and consumes less than 0.5 µA of quiescent current (typical). To activate, or enable, the device, the voltage at the Enable pin must be from (V–) + 2 V to V+. When active, the power-supply requirements are the same as the OPAx374.