The OPAx191 family (OPA191, OPA2191, and OPA4191) is a new generation of 36-V, e-trim™ operational amplifiers.
These devices offer outstanding dc precision and ac performance, including rail-to-rail input/output, low offset voltage (±5 µV, typ), low offset drift (±0.2 µV/°C, typ), and 2-MHz bandwidth.
Unique features, such as differential input-voltage range to the supply rail, high output current (±65 mA), high capacitive load drive of up to 1 nF, and high slew rate (5 V/µs), make the OPAx191 a robust, high-performance operational amplifier for high-voltage industrial applications.
The OPAx191 family of op amps is available in standard packages and is specified from –40°C to +125°C.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
OPA191 | SOIC (8) | 4.90 mm × 3.90 mm |
SOT (5) | 2.90 mm × 1.60 mm | |
VSSOP (8) | 3.00 mm × 3.00 mm | |
OPA2191 | SOIC (8) | 4.90 mm × 3.90 mm |
VSSOP (8) | 3.00 mm × 3.00 mm | |
OPA4191 | SOIC (14) | 8.65 mm x 3.90 mm |
TSSOP (14) | 5.00 mm x 4.40 mm | |
WQFN (16) | 4.00 mm x 4.00 mm |
Changes from Revision C (October 2019) to Revision D (August 2021)
Changes from Revision B (July 2019) to Revision C (October 2019)
Changes from Revision A (April 2016) to Revision B (July 2019)
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | OPA191 | |||
D
(SOIC), DGK (VSSOP) |
DBV (SOT) | |||
+IN | 3 | 3 | I | Noninverting input |
–IN | 2 | 4 | I | Inverting input |
NC | 1, 5, 8 | — | — | No internal connection (can be left floating) |
OUT | 6 | 1 | O | Output |
V+ | 7 | 5 | — | Positive (highest) power supply |
V– | 4 | 2 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | OPA2191 | OPA4191 | |||
D
(SOIC), DGK (VSSOP) |
D
(SOIC), PW (TSSOP) |
RUM (QFN) | |||
+IN A | 3 | 3 | 2 | I | Noninverting input, channel A |
+IN B | 5 | 5 | 4 | I | Noninverting input, channel B |
+IN C | — | 10 | 9 | I | Noninverting input, channel C |
+IN D | — | 12 | 11 | I | Noninverting input, channel D |
–IN A | 2 | 2 | 1 | I | Inverting input, channel A |
–IN B | 6 | 6 | 5 | I | Inverting input, channel B |
–IN C | — | 9 | 8 | I | Inverting input,,channel C |
–IN D | — | 13 | 12 | I | Inverting input, channel D |
OUT A | 1 | 1 | 15 | O | Output, channel A |
OUT B | 7 | 7 | 6 | O | Output, channel B |
OUT C | — | 8 | 7 | O | Output, channel C |
OUT D | — | 14 | 14 | O | Output, channel D |
V+ | 8 | 4 | 3 | — | Positive (highest) power supply |
V– | 4 | 11 | 10 | — | Negative (lowest) power supply |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Supply voltage, VS = (V+) – (V–) | ±20 (+40, single supply) |
V | |||
Signal input pins | Voltage | Common-mode | (V–) – 0.5 | (V+) + 0.5 | V |
Differential | (V+) – (V–) + 0.2 | ||||
Current | ±10 | mA | |||
Output short circuit(2) | Continuous | Continuous | Continuous | ||
Temperature | Operating | –40 | 150 | °C | |
Junction | 150 | ||||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
Charged-device model (CDM), per JEDEC specification JESD22-C101(2), OPA4191IPW package only | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Supply voltage, VS = (V+) – (V–) | 4.5 (±2.25) | 36 (±18) | V | ||
Specified temperature | –40 | 125 | °C |
THERMAL METRIC(1) | OPA191 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | DGK (VSSOP) | DBV (SOT) | |||
8 PINS | 5 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 115.8 | 180.4 | 158.8 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 60.1 | 67.9 | 60.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 56.4 | 102.1 | 44.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 12.8 | 10.4 | 1.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 55.9 | 100.3 | 4.2 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | N/A | N/A | N/A | °C/W |
THERMAL METRIC(1) | OPA2191 | UNIT | ||
---|---|---|---|---|
D (SOIC) | DGK (VSSOP) | |||
8 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 107.9 | 158 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 53.9 | 48.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 48.9 | 78.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 6.6 | 3.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 48.3 | 77.3 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | N/A | N/A | °C/W |
THERMAL METRIC(1) | OPA4191 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | PW (TSSOP) | RUM (QFN) | |||
14 PINS | 16 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 86.4 | 108.1 | 33.0 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 46.3 | 26.3 | 25.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 41.0 | 54.4 | 11.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 11.3 | 1.4 | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 40.7 | 53.3 | 11.5 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | N/A | N/A | 2.6 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | |||||||
VOS | Input offset voltage | VS = ±18 V | ±5 | ±25 | µV | ||
TA = 0°C to 85°C | ±8 | ±75 | |||||
TA = –40°C to +125°C | ±10 | ±125 | |||||
(V+) – 3.0 V < VCM < (V+) – 1.5 V | See Typical Characteristics | ||||||
VS = ±18 V, VCM = (V+) – 1.5 V |
±10 | ±50 | |||||
TA = 0°C to 85°C | ±25 | ±150 | |||||
TA = –40°C to +125°C | ±50 | ±250 | |||||
OPA4191 (RUM, PW), VS = ±18 V VCM = (V+) – 1.5 V |
±5 | ±50 | |||||
TA = 0°C to 85°C | ±10 | ±475 | |||||
TA = –40°C to +125°C | ±20 | ±740 | |||||
dVOS/dT | Input offset voltage drift | VS = ±18 V, D and PW packages only | TA = 0°C to 85°C | ±0.1 | ±0.8 | µV/°C | |
TA = –40°C to +125°C | ±0.15 | ±1.2 | |||||
VS = ±18 V, RUM, DGK and DBV packages only | TA = 0°C to 85°C | ±0.1 | ±0.9 | ||||
TA = –40°C to +125°C | ±0.15 | ±1.3 | |||||
VS = ±18 V, VCM = (V+) – 1.5 V | TA = –40°C to +125°C | ±0.5 | |||||
PSRR | Power-supply rejection ratio | TA = –40°C to +125°C | ±0.3 | ±1.0 | µV/V | ||
INPUT BIAS CURRENT | |||||||
IB | Input bias current | ±5 | ±20 | pA | |||
TA = –40°C to +125°C | ±9 | nA | |||||
IOS | Input offset current | ±2 | ±20 | pA | |||
TA = –40°C to +125°C | ±2 | nA | |||||
NOISE | |||||||
En | Input voltage noise | (V–) – 0.1 V < VCM < (V+) – 3 V | f = 0.1 Hz to 10 Hz | 1.4 | µVPP | ||
(V+) – 1.5 V < VCM < (V+) + 0.1 V | f = 0.1 Hz to 10 Hz | 7 | |||||
en | Input voltage noise density | (V–) – 0.1 V < VCM < (V+) – 3 V | f = 100 Hz | 18 | nV/√Hz | ||
f = 1 kHz | 15 | ||||||
(V+) – 1.5 V < VCM < (V+) + 0.1 V | f = 100 Hz | 53 | |||||
f = 1 kHz | 24 | ||||||
in | Input current noise density | f = 1 kHz | 1.5 | fA/√Hz | |||
INPUT VOLTAGE | |||||||
VCM | Common-mode voltage range | (V–) – 0.1 | (V+) + 0.1 | V | |||
CMRR | Common-mode rejection ratio | VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 3 V |
120 | 140 | dB | ||
VS = ±18 V, (V–) < VCM < (V+) – 3 V |
TA = –40°C to +125°C | 114 | 126 | ||||
VS = ±18 V, (V+) – 1.5 V < VCM < (V+) |
96 | 120 | |||||
TA = –40°C to +125°C | 86 | 100 | |||||
(V+) – 3 V < VCM < (V+) – 1.5 V | See Typical Characteristics | ||||||
INPUT IMPEDANCE | |||||||
ZID | Differential | 100 || 1.6 | MΩ || pF | ||||
ZIC | Common-mode | 1 || 6.4 | 1013Ω || pF | ||||
OPEN-LOOP GAIN | |||||||
AOL | Open-loop voltage gain | VS = ±18 V, (V–) + 0.6 V < VO < (V+) – 0.6 V, RL = 2 kΩ |
124 | 134 | dB | ||
VS = ±18 V, (V–) + 0.8 V < VO < (V+) – 0.8 V, RL = 2 kΩ, RUM package |
124 | 134 | |||||
VS = ±18 V, (V–) + 0.6 V < VO < (V+) – 0.6 V, RL = 2 kΩ |
TA = –40°C to +125°C | 114 | 126 | ||||
VS = ±18 V, (V–) + 0.8 V < VO < (V+) – 0.8 V, RL = 2 kΩ, RUM package |
TA = –40°C to +125°C | 114 | 126 | ||||
VS = ±18 V, (V–) + 0.3 V < VO < (V+) – 0.3 V, RL = 10 kΩ |
126 | 140 | |||||
VS = ±18 V, (V–) + 0.3 V < VO < (V+) – 0.3 V, RL = 10 kΩ |
TA = –40°C to +125°C | 120 | 134 | ||||
FREQUENCY RESPONSE | |||||||
GBW | Unity gain bandwidth | 2.5 | MHz | ||||
SR | Slew rate | VS = ±18 V, G = 1, 10-V step | Falling | 7.5 | V/µs | ||
Rising | 5.5 | ||||||
ts | Settling time | To 0.01%, CL = 20 pF | VS = ±18 V, G = 1, 2-V step | 0.7 | µs | ||
VS = ±18 V, G = 1, 5-V step | 1 | ||||||
To 0.001%, CL = 20 pF | VS = ±18 V, G = 1, 2-V step | 1.8 | |||||
VS = ±18 V, G = 1, 5-V step | 3.7 | ||||||
tOR | Overload recovery time | VIN × G = VS | From overload to negative rail | 0.4 | µs | ||
From overload to positive rail | 1 | ||||||
THD+N | Total harmonic distortion + noise | G = 1, f = 1 kHz, VO = 3.5 VRMS | 0.0012% | ||||
Crosstalk | OPA2191 and OPA4191, at dc | 150 | dB | ||||
OPA2191 and OPA4191, f = 100 kHz | 130 | dB | |||||
OUTPUT | |||||||
VO | Voltage output swing from rail | Positive rail | No load | 5 | 15 | mV | |
RL = 10 kΩ | 50 | 110 | |||||
RL = 2 kΩ | 200 | 500 | |||||
Negative rail | No load | 5 | 15 | ||||
RL = 10 kΩ | 50 | 110 | |||||
RL = 2 kΩ | 200 | 500 | |||||
ISC | Short-circuit current | VS = ±18 V | ±65 | mA | |||
CL | Capacitive load drive | See Typical Characteristics | |||||
ZO | Open-loop output impedance | f = 1 MHz, IO = 0 A, See Typical Characteristics | 700 | Ω | |||
POWER SUPPLY | |||||||
IQ | Quiescent current per amplifier | IO = 0 A | 140 | 200 | µA | ||
TA = –40°C to +125°C | 250 | ||||||
TEMPERATURE | |||||||
Thermal protection | 180 | °C | |||||
Thermal hysteresis | 30 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | |||||||
VOS | Input offset voltage | VS = ±2.25 V, VCM = (V+) – 3 V |
±5 | ±25 | µV | ||
TA = 0°C to 85°C | ±8 | ±75 | |||||
TA = –40°C to +125°C | ±10 | ±125 | |||||
(V+) – 3.0 V < VCM < (V+) – 1.5 V | See Typical Characteristics | ||||||
VS = ±3 V, VCM = (V+) – 1.5 V |
±10 | ±50 | |||||
TA = 0°C to 85°C | ±25 | ±150 | |||||
TA = –40°C to +125°C | ±50 | ±250 | |||||
OPA4191 (RUM, PW), VS = ±3 V, VCM = (V+) – 1.5 V |
±10 | ±50 | |||||
TA = –40°C to +85°C | ±90 | ±475 | |||||
TA = –40°C to +125°C | ±150 | ±740 | |||||
dVOS/dT | Input offset voltage drift | VS = ±2.25 V, VCM = (V+) – 3 V, D and PW packages only |
TA = 0°C to 85°C | ±0.1 | ±0.8 | µV/°C | |
TA = –40°C to +125°C | ±0.15 | ±1.2 | µV/°C | ||||
VS = ±2.25 V, VCM = (V+) – 3 V, RUM, DGK and DBV packages only | TA = 0°C to 85°C | ±0.1 | ±0.9 | µV/°C | |||
TA = –40°C to +125°C | ±0.15 | ±1.3 | |||||
VS = ±2.25 V, VCM = (V+) – 1.5 V | TA = –40°C to +125°C | ±0.5 | |||||
PSRR | Power-supply rejection ratio | TA = –40°C to +125°C, VCM = VS / 2 – 0.75 V | ±1 | µV/V | |||
INPUT BIAS CURRENT | |||||||
IB | Input bias current | ±5 | ±20 | pA | |||
TA = –40°C to +125°C | ±9 | nA | |||||
IOS | Input offset current | ±2 | ±20 | pA | |||
TA = –40°C to +125°C | ±2 | nA | |||||
NOISE | |||||||
En | Input voltage noise | (V–) – 0.1 V < VCM < (V+) – 3 V | f = 0.1 Hz to 10 Hz | 1.4 | µVPP | ||
(V+) – 1.5 V < VCM < (V+) + 0.1 V | f = 0.1 Hz to 10 Hz | 7 | |||||
en | Input voltage noise density | (V–) – 0.1 V < VCM < (V+) – 3 V | f = 100 Hz | 18 | nV/√Hz | ||
f = 1 kHz | 15 | ||||||
(V+) – 1.5 V < VCM < (V+) + 0.1 V | f = 100 Hz | 53 | |||||
f = 1 kHz | 24 | ||||||
in | Input current noise density | f = 1 kHz | 1.5 | fA/√Hz | |||
INPUT VOLTAGE | |||||||
VCM | Common-mode voltage range | (V–) – 0.1 | (V+) + 0.1 | V | |||
CMRR | Common-mode rejection ratio | VS = ±2.25 V, (V–) – 0.1 V < VCM < (V+) – 3 V |
96 | 110 | dB | ||
VS = ±2.25 V, (V–) < VCM < (V+) – 3 V |
TA = –40°C to +125°C | 90 | 104 | ||||
VS = ±2.25 V, (V+) – 1.5 V < VCM < (V+) |
96 | 120 | |||||
TA = –40°C to +125°C | 84 | 100 | |||||
(V+) – 3 V < VCM < (V+) – 1.5 V | See Typical Characteristics | ||||||
INPUT IMPEDANCE | |||||||
ZID | Differential | 100 || 1.6 | MΩ || pF | ||||
ZIC | Common-mode | 1 || 6.4 | 1013Ω || pF | ||||
OPEN-LOOP GAIN | |||||||
AOL | Open-loop voltage gain | VS = ±2.25 V, (V–) + 0.6 V < VO < (V+) – 0.6 V, RL = 2 kΩ |
110 | 120 | dB | ||
TA = –40°C to +125°C | 100 | 114 | |||||
VS = ±2.25 V, (V–) + 0.3 V < VO < (V+) – 0.3 V, RL = 10 kΩ |
110 | 126 | |||||
TA = –40°C to +125°C | 106 | 120 | |||||
FREQUENCY RESPONSE | |||||||
GBW | Unity gain bandwidth | 2.2 | MHz | ||||
SR | Slew rate | VS = ±2.25 V, G = 1, 1-V step | Falling | 6.5 | V/µs | ||
Rising | 5.5 | ||||||
tOR | Overload recovery time | VIN × G = VS | From overload to negative rail | 0.4 | µs | ||
From overload to positive rail | 1 | ||||||
Crosstalk | OPA2191 and OPA4191, at dc | 150 | dB | ||||
OPA2191 and OPA4191, f = 100 kHz | 130 | dB | |||||
OUTPUT | |||||||
VO | Voltage output swing from rail | Positive rail | No load | 5 | 15 | mV | |
RL = 10 kΩ | 15 | 110 | |||||
RL = 2 kΩ | 60 | 500 | |||||
Negative rail | No load | 5 | 15 | ||||
RL = 10 kΩ | 15 | 110 | |||||
RL = 2 kΩ | 60 | 500 | |||||
ISC | Short-circuit current | VS = ±2.25 V | ±30 | mA | |||
CL | Capacitive load drive | See Typical Characteristics | |||||
ZO | Open-loop output impedance | f = 1 MHz, IO = 0 A, see Typical Characteristics | 700 | Ω | |||
POWER SUPPLY | |||||||
IQ | Quiescent current per amplifier | IO = 0 A | 140 | 200 | µA | ||
TA = –40°C to +125°C | 250 | ||||||
TEMPERATURE | |||||||
Thermal protection | 180 | °C | |||||
Thermal hysteresis | 30 | °C |
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
DESCRIPTION | FIGURE |
---|---|
Offset Voltage Production Distribution | Figure 6-1, Figure 6-2, Figure 6-3, Figure 6-4, Figure 6-5, Figure 6-6 |
Offset Voltage Drift Distribution | Figure 6-7, Figure 6-8, |
Offset Voltage vs Temperature | Figure 6-9, Figure 6-10 |
Offset Voltage vs Common-Mode Voltage | Figure 6-11, Figure 6-12 |
Offset Voltage vs Power Supply | Figure 6-13 |
Open-Loop Gain and Phase vs Frequency | Figure 6-14 |
Closed-Loop Gain and Phase vs Frequency | Figure 6-15 |
Input Bias Current vs Common-Mode Voltage | Figure 6-16 |
Input Bias Current vs Temperature | Figure 6-17 |
Output Voltage Swing vs Output Current (maximum supply) | Figure 6-18, Figure 6-19 |
CMRR and PSRR vs Frequency | Figure 6-20 |
CMRR vs Temperature | Figure 6-21 |
PSRR vs Temperature | Figure 6-22 |
0.1-Hz to 10-Hz Noise | Figure 6-23 |
Input Voltage Noise Spectral Density vs Frequency | Figure 6-24 |
THD+N Ratio vs Frequency | Figure 6-25 |
THD+N vs Output Amplitude | Figure 6-26 |
Quiescent Current vs Supply Voltage | Figure 6-27 |
Quiescent Current vs Temperature | Figure 6-28 |
Open Loop Gain vs Temperature | Figure 6-29, Figure 6-30 |
Open Loop Output Impedance vs Frequency | Figure 6-31 |
Small Signal Overshoot vs Capacitive Load (100-mV output step) | Figure 6-32, Figure 6-33 |
No Phase Reversal | Figure 6-34 |
Overload Recovery | Figure 6-35 |
Small-Signal Step Response (100 mV) | Figure 6-36, Figure 6-37 |
Large-Signal Step Response | Figure 6-38, Figure 6-39 |
Settling Time | Figure 6-40, Figure 6-41, Figure 6-42, Figure 6-43 |
Short-Circuit Current vs Temperature | Figure 6-44 |
Maximum Output Voltage vs Frequency | Figure 6-45 |
Propagation Delay Rising Edge | Figure 6-46 |
Propagation Delay Falling Edge | Figure 6-47 |
TA = 25°C |
TA = 85°C |
TA = –25°C |
TA = –40°C to +125°C, SOIC package |
Statistical distribution |
30 typical units |
Sinking |
RL = 10 kΩ |
G = –1, 100-mV output step |
VS = ±18 V, G = –10 V/V |
G = –1, RL = 1 kΩ, CL = 10 pF |
G = –1, RL = 1 kΩ, CL = 10 pF |
Gain = 1, 2-V step, falling, step applied at t = 0 µs |
Gain = 1, 5-V step, falling, step applied at t = 0 µs |
TA = 125°C |
TA = 0°C |
TA = –40°C |
TA = 0°C to 85°C, SOIC package |
4 typical units |
Sourcing |
RL = 2 kΩ |
G = 1, 100-mV output step |
G = 1, CL = 10 pF |
G = 1, CL = 10 pF |
Gain = 1, 2-V step, rising, step applied at t = 0 µs |
Gain = 1, 5-V step, rising, step applied at t = 0 µs |
The OPAx191 family of operational amplifiers is manufactured using TI’s e-trim operation amplifier technology. This e-trim operational amplifier technology is a TI proprietary method of trimming internal device parameters during either wafer probing or final testing. Each amplifier input offset voltage and input offset voltage drift is trimmed in production, thereby minimizing errors associated with input offset voltage and input offset voltage drift. When trimming input offset voltage drift, the systematic or linear drift error on each device is trimmed to zero. Figure 7-1 illustrates this concept.
A common method of specifying input offset voltage drift is the box method. The box method estimates a maximum input offset drift by bounding an offset voltage versus temperature curve with a box and using the corners of this bounding box to determine the drift. The slope of the line connecting the diagonal corners of the box corresponds to the input offset voltage drift. Figure 7-2 illustrates the box method concept. The box method works particularly well when the input offset drift is dominated by the linear component of drift, but because the OPA191 family uses TI’s e-trim operational amplifier technology to remove the linear component input offset voltage drift, the box method is not a particularly useful method of accurately performing an error analysis. Shown in Figure 7-2 are 30 typical units of OPAx191 with the box method superimposed for illustrative purposes. The boundaries of the box are determined by the specified temperature range along the x-axis and the maximum specified input offset voltage across that same temperature range along the y-axis. Using the box method predicts an input offset voltage drift of 0.9 µV/°C. As shown in Figure 7-2, the slopes of the actual input offset voltage versus temperature are much less than that predicted by the box method. The box method predicts a pessimistic value for the maximum input offset voltage drift and is not recommended when performing an error analysis.
Instead of the box method, a convenient way to illustrate input offset drift is to compute the slopes of the input offset voltage versus temperature curve. This is the same as computing the input offset drift at each point along the input offset voltage versus temperature curve. The results for the OPAx191 family are illustrated in Figure 7-3.
As illustrated in Figure 7-3, the input offset drift is typically less than ±0.3 µV/°C over the range from –40°C to +125°C. When performing an error analysis over the full specified temperature range, use the typical and maximum values for input offset voltage drift as described in the Electrical Characteristics tables. If a reduced temperature range is applicable, use the information illustrated in Figure 7-3 when performing an error analysis. To determine the change in input offset voltage, use Equation 1:
where
For example, determine the amount of OPA191ID input offset voltage change over the temperature range of 25°C to 75°C for 1 σ (68%) of the units. As shown in Figure 7-3, the input offset drift is typically 0.25 µV/°C. This input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.25 µV/°C = 12.5 µV.
For 3 σ (99.7%) of the units, Figure 7-3 shows a typical input offset drift of approximately 0.75 µV/°C. This input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.75 µV/°C = 37.5 µV.
The OPAx191 family of e-trim operational amplifiers use a method of package-level trim for offset and offset temperature drift implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points are set, further communication to the trim structure is permanently disabled. Section 8.2 shows the simplified diagram of the OPAx191.
Unlike previous e-trim operational amplifiers, the OPAx191 uses a patented two-temperature trim architecture to achieve a very low offset voltage and low voltage offset drift over the full specified temperature range. This level of precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial sensors, filters, and high-voltage data acquisition.
The OPAx191 uses a unique input architecture to eliminate the need for input protection diodes but still provides robust input protection under transient conditions. Conventional input diode protection schemes shown in Figure 8-1 can be activated by fast transient step responses and can introduce signal distortion and settling time delays because of alternate current paths, as shown in Figure 8-2. For low-gain circuits, these fast-ramping input signals forward-bias back-to-back diodes that cause an increase in input current, resulting in extended settling time.
The OPAx191 family of operational amplifiers provides a true high-impedance differential input capability for high-voltage applications. This patented input protection architecture does not introduce additional signal distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications. The OPAx191 tolerates a maximum differential swing (voltage between inverting and noninverting pins of the op amp) of up to 36 V, making the device an excellent choice for use as a comparator or in applications with fast-ramping input signals such as multiplexed data-acquisition systems (see Figure 9-4).
The OPAx191 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx191 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 8-3 shows the results of this testing on the OPAx191. Table 8-1 shows the EMIRR IN+ values for the OPAx191 at particular frequencies commonly encountered in real-world applications. Applications listed in Table 8-1 may be centered on or operated near the particular frequency shown. Detailed information can also be found in the EMI Rejection Ratio of Operational Amplifiers application report , available for download from www.ti.com.
PRF = –10 dBm, VS = ±15 V, VCM = 0 V |
FREQUENCY | APPLICATION OR ALLOCATION | EMIRR IN+ |
---|---|---|
400 MHz | Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications | 36 dB |
900 MHz | Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications | 45 dB |
1.8 GHz | GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) | 57 dB |
2.4 GHz | 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) | 62 dB |
3.6 GHz | Radiolocation, aero communication and navigation, satellite, mobile, S-band | 76 dB |
5.0 GHz | 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) | 86 dB |
The OPAx191 family has internal phase-reversal protection. Many op amps exhibit phase reversal when the input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The OPAx191 is a rail-to-rail input op amp, and therefore the common-mode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into the appropriate rail. This performance is shown in Figure 8-4.
The internal power dissipation of any amplifier causes the internal (junction) temperature to rise. This phenomenon is called self heating. The OPAx191 has a thermal protection feature that prevents damage from self heating.
This thermal protection works by monitoring the temperature of the output stage and turning off the op amp output drive for temperatures above approximately 180°C. Thermal protection forces the output to a high-impedance state. The OPAx191 is also designed with approximately 30°C of thermal hysteresis. Thermal hysteresis prevents the output stage from cycling in and out of the high-impedance state. The OPAx191 returns to normal operation when the output stage temperature falls below approximately 150°C.
The absolute maximum junction temperature of the OPAx191 is 150°C. Exceeding the limits shown in Section 6.1 may cause damage to the device. Thermal protection triggers at 180°C because of unit-to-unit variance, but does not interfere with device operation up to the absolute maximum ratings. This thermal protection is not designed to prevent this device from exceeding absolute maximum ratings, but rather from excessive thermal overload.
The OPAx191 features a patented output stage capable of driving large capacitive loads, and in a unity-gain configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 8-5. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier will be stable in operation.
Like many low-power amplifiers, some ringing can occur even with capacitive loads less than 100 pF. In unity-gain configurations with no or very light dc loads, place an RC snubber circuit at the OPAx191 output to reduce any possibility of ringing in lightly-loaded applications. Figure 8-6 illustrates the recommended RC snubber circuit.
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small,
10-Ω to 20-Ω resistor (RISO) in series with the output, as shown in Figure 8-7. This resistor significantly reduces ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load in parallel with the capacitive load, a voltage divider is created, introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive makes the OPA191 a great choice for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 8-7 uses RISO to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin. Results using the OPA191 are summarized in Table 8-2. For additional information on techniques to optimize and design using this circuit, TI Precision Design TIPD128, Capacitive Load Drive Verified Reference Design Using an Isolation Resistor, details complete design goals, simulation, and test results.
PARAMETER | VALUE | ||||||||
---|---|---|---|---|---|---|---|---|---|
Capacitive Load | 100 pF | 1000 pF | 0.01 µF | 0.1 µF | 1 µF | ||||
Phase Margin | 45° | 45° | 60° | 45° | 60° | 45° | 60° | 45° | 60° |
RISO (Ω) | 280 | 113 | 432 | 68 | 210 | 17.8 | 53.6 | 3.6 | 10 |
Measured Overshoot (%) | 23 | 23 | 8 | 23 | 8 | 23 | 8 | 23 | 8 |
The OPAx191 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and P-channel differential input pairs, as shown in Figure 8-8. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition region, typically ( V+) –3 V to (V+) – 1.5 V in which both input pairs are active. This transition region varies modestly with process variation. Within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance are degraded compared to operation outside this region.
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when possible. The OPAx191 uses a precision trim for both the N-channel and P-channel regions. This technique enables significantly lower levels of offset than previous-generation devices, causing variance in the transition region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown in Figure 8-9.
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress (EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. See Figure 8-10 for an illustration of the ESD circuits contained in the OPAx191 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event is very high voltage for a very short duration (for example, 1 kV for 100 ns); whereas, an EOS event is lower voltage for a longer duration (for example, 50 V for 100 ms). The ESD diodes are designed for out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit labeled ESD power-supply circuit. The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if activated in-circuit. A transient voltage suppressor (TVS) can be used to prevent against damage caused by turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.