Refer to the PDF data sheet for device specific package drawings
The OPA330 series of CMOS operational amplifiers offer precision performance at a very competitive price. These devices are members of the Zero-Drift family of amplifiers which use a proprietary auto-calibration technique to simultaneously provide low offset voltage (50-μV maximum) and near-zero drift over time and temperature at only 35 μA (maximum) of quiescent current. The OPA330 family features rail-to-rail input and output in addition to near-flat 1/f noise, making this amplifier ideal for many applications and much easier to design into a system. These devices are optimized for low-voltage operation as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V).
The OPA330 (single version) is available in the 5-pin DSBGA, 5-pin SC70, 5-pin SOT-23, and 8-pin SOIC packages. The OPA2330 (dual version) is offered in 3 mm × 3 mm, 8-pin SON, 8-pin VSSOP, and 8-pin SOIC packages. The OPA4330 is offered in the standard 14-pin SOIC and 14-pin TSSOP packages, as well as in the space-saving 14-pin VQFN package. All versions are specified for operation from –40°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
OPA330 | SOIC (8) | 4.90 mm × 3.91 mm |
SOT (5) | 2.90 mm × 1.60 mm | |
SC70 (5) | 2.00 mm × 1.25 mm | |
DSBGA (5) | 0.00 mm × 0.00 mm | |
OPA2330 | SOIC (8) | 4.90 mm × 3.91 mm |
VSSOP (8) | 3.00 mm × 3.00 mm | |
SON (8) | 3.00 mm × 3.00 mm | |
OPA4330 | SOIC (14) | 8.65 mm × 3.91 mm |
TSSOP (14) | 5.00 mm × 4.40 mm | |
VQFN (14) | 3.50 mm × 3.50 mm |
Changes from F Revision (June 2016) to G Revision
Changes from E Revision (February 2011) to F Revision
Changes from D Revision (June 2010) to E Revision
Changes from C Revision (October 2009) to D Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOIC, VSSOP |
SON | ||
–IN A | 2 | 2 | I | Negative (inverting) input signal, channel A |
+IN A | 3 | 3 | I | Positive (noninverting) input signal, channel A |
–IN B | 6 | 6 | I | Negative (inverting) input signal, channel B |
+IN B | 5 | 5 | I | Positive (noninverting) input signal, channel B |
OUT A | 1 | 1 | O | Output channel A |
OUT B | 7 | 7 | O | Output channel B |
V– | 4 | 4 | — | Negative (lowest) power supply |
V+ | 8 | 8 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | SOIC | TSSOP | VQFN | ||
–IN A | 2 | 2 | 2 | I | Negative (inverting) input signal, channel A |
+IN A | 3 | 3 | 3 | I | Positive (noninverting) input signal, channel A |
–IN B | 6 | 6 | 6 | I | Negative (inverting) input signal, channel B |
+IN B | 5 | 5 | 5 | I | Positive (noninverting) input signal, channel B |
–IN C | 9 | 9 | 9 | I | Negative (inverting) input signal, channel C |
+IN C | 10 | 10 | 10 | I | Positive (noninverting) input signal, channel C |
–IN D | 13 | 13 | 13 | I | Negative (inverting) input signal, channel D |
+IN D | 12 | 12 | 12 | I | Positive (noninverting) input signal, channel D |
OUT A | 1 | 1 | 1 | O | Output channel A |
OUT B | 7 | 7 | 7 | O | Output channel B |
OUT C | 8 | 8 | 8 | O | Output channel C |
OUT D | 14 | 14 | 14 | O | Output channel D |
V– | 11 | 11 | 11 | — | Negative (lowest) power supply |
V+ | 4 | 4 | 4 | — | Positive (highest) power supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | Supply, VS = (V+) – (V–) | 7 | V | |
Signal input terminals(2) (TBD should terminal be pin?) | (V–) –0.3 | (V+) + 0.3 | V | |
Current | Signal input terminals(2) | –10 | 10 | mA |
Output short-circuit(3) | Continuous | |||
Temperature | Operating range, TA | –40 | 150 | °C |
Junction, TJ | 150 | °C | ||
Storage, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
Machine model (MM) | ±400 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
(V+) – (V–) | Supply voltage | ±0.9 (1.8) | ±2.5 (5) | ±2.75 (5.5) | V |
TA | Specified temperature | –40 | 25 | 125 | °C |
THERMAL METRIC(1) | OPA330 | UNIT | ||||
---|---|---|---|---|---|---|
D (SOIC) | DBV (SOT-23) | DCK (SC70) | YFF (DSBGA) | |||
8 PINS | 5 PINS | 5 PINS | 5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 140.1 | 220.8 | 298.4 | 130 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 89.8 | 97.5 | 65.4 | 54 | °C/W |
RθJB | Junction-to-board thermal resistance | 80.6 | 61.7 | 97.1 | 51 | °C/W |
ψJT | Junction-to-top characterization parameter | 28.7 | 7.6 | 0.8 | 1 | °C/W |
ψJB | Junction-to-board characterization parameter | 80.1 | 61.1 | 95.5 | 50 | °C/W |
THERMAL METRIC(1) | OPA2330 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | DGK (VSSOP) | DRB (SON) | |||
8 PINS | 8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 124 | 180.3 | 46.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 73.7 | 48.1 | 26.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 64.4 | 100.9 | 22.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 18 | 2.4 | 1.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 63.9 | 99.3 | 22.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | 10.1 | °C/W |
THERMAL METRIC(1) | OPA4330 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | PW (TSSOP) | RGY (VQFN) | |||
14 PINS | 14 PINS | 14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 83.8 | 120.8 | 49.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 70.7 | 34.3 | 75.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 59.5 | 62.8 | 61.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 11.6 | 1 | 1.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 37.7 | 56.5 | 19.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | 4.6 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | ||||||||
VOS | Input offset voltage | VS = 5 V | 8 | 50 | µV | |||
dVOS/dT | Input offset voltage versus temperature | At TA = –40°C to +125°C | 0.02 | 0.25 | µV/°C | |||
PSRR | Input offset voltage versus power supply | At TA = –40°C to +125°C | 1 | 10 | µV/V | |||
Long-term stability(1) | VS = 1.8 V to 5.5 V | See (1) | ||||||
Channel separation, dc | 0.1 | µV/V | ||||||
INPUT BIAS CURRENT | ||||||||
IB | Input bias current | At 25°C | ±200 | ±500 | pA | |||
OPA330YFF, OPA4330 | ±70 | ±300 | pA | |||||
At TA = –40°C to +125°C | ±300 | pA | ||||||
IOS | Input offset current | At 25°C | ±400 | ±1000 | pA | |||
OPA330YFF, OPA4330 | ±140 | ±600 | pA | |||||
NOISE | ||||||||
en | Input voltage noise density | f = 1 kHz | 55 | nV/√Hz | ||||
Input voltage noise | f = 0.01 Hz to 1 Hz | 0.3 | µVPP | |||||
f = 0.1 Hz to 10 Hz | 1.1 | µVPP | ||||||
in | Input current noise | f = 10 Hz | 100 | fA/√Hz | ||||
INPUT VOLTAGE RANGE | ||||||||
VCM | Common-mode voltage range | (V–) – 0.1 | (V+) + 0.1 | V | ||||
CMRR | Common-mode rejection ratio | At TA = –40°C to +125°C, (V–) – 0.1 V < VCM < (V+) + 0.1 V |
100 | 115 | dB | |||
At TA = –40°C to +125°C, (V–) – 0.1 V < VCM < (V+) + 0.1 V, VS = 5.5 V |
100 | 115 | dB | |||||
OPA330YFF, OPA4330 | 100 | 115 | dB | |||||
INPUT CAPACITANCE | ||||||||
Differential | 2 | pF | ||||||
Common-mode | 4 | pF | ||||||
OPEN-LOOP GAIN | ||||||||
AOL | Open-loop voltage gain | At TA = –40°C to +125°C, (V–) + 100 mV < VO < (V+) – 100 mV, RL = 10 kΩ |
100 | 115 | dB | |||
FREQUENCY RESPONSE | ||||||||
GBW | Gain-bandwidth product | CL = 100 pF | 350 | kHz | ||||
SR | Slew rate | G = +1 | 0.16 | V/µs | ||||
OUTPUT | ||||||||
Voltage output swing from rail | At TA = –40°C to +125°C | 30 | 100 | mV | ||||
ISC | Short-circuit current | ±5 | mA | |||||
CL | Capacitive load drive | See Typical Characteristics | ||||||
Open-loop output impedance | f = 350 kHz, IO = 0 mA | 2 | kΩ | |||||
POWER SUPPLY | ||||||||
VS | Specified voltage range | 1.8 | 5.5 | V | ||||
IQ | Quiescent current per amplifier | At TA = –40°C to +125°C, IO = 0 mA | 21 | 35 | µA | |||
Turnon time | VS = 5 V | 100 | µs |
DESCRIPTION | FIGURE NO. | |
---|---|---|
Offset Voltage Production Distribution | Figure 1 | |
Open-Loop Gain vs Frequency | Figure 2 | |
Common-Mode Rejection Ratio vs Frequency | Figure 3 | |
Power-Supply Rejection Ratio vs Frequency | Figure 4 | |
Output Voltage Swing vs Output Current | Figure 5 | |
Input Bias Current vs Common-Mode Voltage | Figure 6 | |
Input Bias Current vs Temperature | Figure 7 | |
Quiescent Current vs Temperature | Figure 8 | |
Large-Signal Step Response | Figure 9 | |
Small-Signal Step Response | Figure 10 | |
Positive Overvoltage Recovery | Figure 11 | |
Negative Overvoltage Recovery | Figure 12 | |
Settling Time vs Closed-Loop Gain | Figure 13 | |
Small-Signal Overshoot vs Load Capacitance | Figure 14 | |
0.1-Hz to 10-Hz Noise | Figure 15 | |
Current and Voltage Noise Spectral Density vs Frequency | Figure 16 | |
Input Bias Current vs Input Differential Voltage | Figure 17 |