SLES254D April   2010  – July 2015 PCM1753-Q1 , PCM1754-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Clock Input Timing
    7. 7.7 Audio Interface Timing
    8. 7.8 Control Interface Timing Requirements
    9. 7.9 Typical Characteristics
      1. 7.9.1 Digital Filter (De-Emphasis Off)
      2. 7.9.2 Analog Dynamic Performance (Supply Voltage Characteristics)
      3. 7.9.3 Analog Dynamic Performance (Temperature Characteristics)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 System Clock and Reset Functions
        1. 8.3.1.1 System Clock Input
        2. 8.3.1.2 Power-On Reset Functions
      2. 8.3.2 Audio Serial Interface
        1. 8.3.2.1 Audio Data Formats and Timing
      3. 8.3.3 Zero Flag (PCM1754-Q1)
      4. 8.3.4 Zero Flag (PCM1753-Q1)
      5. 8.3.5 Zero Flag Outputs
      6. 8.3.6 Analog Outputs
        1. 8.3.6.1 VCOM Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Control (PCM1754-Q1)
      2. 8.4.2 Oversampling Rate Control (PCM1754-Q1)
    5. 8.5 Programming
      1. 8.5.1 Software Control (PCM1753-Q1)
        1. 8.5.1.1 Register Write Operation
    6. 8.6 Register Maps
      1. 8.6.1 Mode Control Registers (PCM1753-Q1)
        1. 8.6.1.1 User-Programmable Mode Controls
        2. 8.6.1.2 Register Definitions
          1. 8.6.1.2.1  ATx[7:0]: Digital Attenuation Level Setting
          2. 8.6.1.2.2  MUTx: Soft Mute Control
          3. 8.6.1.2.3  OVER: Oversampling Rate Control
          4. 8.6.1.2.4  SRST: Reset
          5. 8.6.1.2.5  DACx: DAC Operation Control
          6. 8.6.1.2.6  DM12: Digital De-Emphasis Function Control
          7. 8.6.1.2.7  DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
          8. 8.6.1.2.8  FMT[2:0]: Audio Interface Data Format
          9. 8.6.1.2.9  FLT: Digital Filter Rolloff Control
          10. 8.6.1.2.10 DREV: Output Phase Select
          11. 8.6.1.2.11 ZREV: Zero Flag Polarity Select
          12. 8.6.1.2.12 AZRO: Zero Flag Function Select
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Supplies and Grounding
        2. 9.2.1.2 DAC Output Filter Circuits
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Total Harmonic Distortion + Noise
        2. 9.2.2.2 Dynamic Range
        3. 9.2.2.3 Idle Channel Signal-to-Noise Ratio (SNR)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • 24-Bit Resolution
  • Analog Performance (VCC = 5 V)
    • Dynamic Range: 106 dB
    • SNR: 106 dB, Typical
    • THD+N: 0.002%, Typical
    • Full-Scale Output: 4 VPP, Typical
  • 4× and 8× Oversampling Digital Filter
    • Stop-Band Attenuation: –50 dB
    • Pass-Band Ripple: ±0.04 dB
  • Sampling Frequency: 5 kHz to 200 kHz
  • System Clock: 128 fS, 192 fS, 256 fS, 384 fS,
    512 fS, 768 fS, 1152 fS with Auto Detect
  • Hardware Control (PCM1754-Q1)
    • I2S and 16-Bit Word, Right-Justified
    • 44.1 kHz Digital De-Emphasis
    • Soft Mute
    • Zero Flag for L-, R-Channel Common Output
  • Power Supply: 5-V Single Supply
  • Small 16-Lead SSOP Package, Lead-Free

2 Applications

  • Automotive Infotainment and Cluster
  • A/V Receivers
  • HDTV Receivers
  • Car Audio Systems
  • Other Applications Requiring 24-Bit Audio

3 Description

The PCM175x-Q1 family of devices is a CMOS, monolithic, integrated circuit, which includes stereo digital-to-analog converters and support circuitry in a small 16-lead SSOP package. The data converters use TI's enhanced multilevel delta-sigma architecture, which employs 4th-order noise shaping and 8-level amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM175x-Q1 family of devices accepts industry-standard audio data formats with 16- to 24-bit data, providing easy interfacing to audio DSP and decoder chips. Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through a three-wire serial control port, which supports register write functions.

The PCM1753-Q1 device is pin-compatible with the PCM1748, PCM1742, and PCM1741 devices, except for pin 5.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
PCM1753-Q1 SSOP (16) 4.90 mm × 3.90 mm
PCM1754-Q1
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

PCM1753-Q1 PCM1754-Q1 fbd_fp_les254.gif