SLAS859C May 2012 – May 2015 PCM5100A , PCM5100A-Q1 , PCM5101A , PCM5101A-Q1 , PCM5102A , PCM5102A-Q1
PRODUCTION DATA.
The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.
Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.
The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.
The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.
Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.
Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
PCM5102A | TSSOP (20) | 5.50 mm × 4.40 mm |
PCM5101A | ||
PCM5100A |
Changes from B Revision (January 2015) to C Revision
Changes from A Revision (September 2012) to B Revision
Changes from * Revision (May 2012) to A Revision
PART NUMBER | DYNAMIC RANGE | SNR | THD |
---|---|---|---|
PCM5102A | 112dB | 112dB | –93 dB |
PCM5101A | 106 dB | 106 dB | –92 dB |
PCM5100A | 100 dB | 100 dB | –90 dB |
PARAMETER | PCM5102 / PCM5101 / PCM5100 |
SNR | 112 / 106 / 100 dB |
Dynamic range | 112 /106 / 100 dB |
THD+N at –1 dBFS | –93/ –92 / –90 dB |
Full-scale single-ended output | 2.1 VRMS (GND center) |
Normal 8× oversampling digital filter latency | 20tS |
Low latency 8× oversampling digital filter latency | 3.5tS |
Sampling frequency | 8 kHz to 384 kHz |
System clock multiples (fSCK): 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072 | Up to 50 MHz |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 9 | — | Analog ground |
AVDD | 8 | P | Analog power supply, 3.3 V |
BCK | 13 | I | Audio data bit clock input(1) |
CAPM | 4 | O | Charge pump flying capacitor terminal for negative rail |
CAPP | 2 | O | Charge pump flying capacitor terminal for positive rail |
CPGND | 3 | — | Charge pump ground |
CPVDD | 1 | P | Charge pump power supply, 3.3 V |
DEMP | 10 | I | De-emphasis control for 44.1-kHz sampling rate(1): Off (Low) / On (High) |
DGND | 19 | — | Digital ground |
DIN | 14 | I | Audio data input(1) |
DVDD | 20 | P | Digital power supply, 1.8 V or 3.3 V |
FLT | 11 | I | Filter select : Normal latency (Low) / Low latency (High) |
FMT | 16 | I | Audio format selection : I2S (Low) / Left-justified (High) |
LDOO | 18 | P | Internal logic supply rail terminal for decoupling, or external 1.8 V supply terminal |
LRCK | 15 | I | Audio data word clock input(1) |
OUTL | 6 | O | Analog output from DAC left channel |
OUTR | 7 | O | Analog output from DAC right channel |
SCK | 12 | I | System clock input(1) |
VNEG | 5 | O | Negative charge pump rail terminal for decoupling, –3.3 V |
XSMT | 17 | I | Soft mute control(1): Soft mute (Low) / soft un-mute (High) |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | AVDD, CPVDD, DVDD | –0.3 | 3.9 | V |
LDO with DVDD at 1.8 V | –0.3 | 2.25 | ||
Digital input voltage | DVDD at 1.8 V | –0.3 | 2.25 | |
DVDD at 3.3 V | –0.3 | 3.9 | ||
Analog input voltage | –0.3 | 3.9 | ||
Operating junction temperature range | –40 | 130 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
AVDD | Analog power supply voltage range | Referenced to AGND(1) | VCOM mode | 3 | 3.3 | 3.46 | V |
VREF mode | 3.2 | 3.3 | 3.46 | ||||
DVDD | Digital power supply voltage range | Referenced to DGND(1) | 1.8 V DVDD | 1.65 | 1.8 | 1.95 | V |
3.3 V DVDD | 3.1 | 3.3 | 3.46 | ||||
CPVDD | Charge pump supply voltage range | Referenced to CPGND(1) | 3.1 | 3.3 | 3.46 | V | |
MCLK | Master clock frequency | 50 | MHz | ||||
LOL, LOR | Stereo line output load resistance | 1 | 10 | kΩ | |||
CLOUT | Digital output load capacitance | 10 | pF | ||||
TJ | Operating junction temperature range | –40 | 130 | °C |
THERMAL METRIC(1) | PW | UNIT | |
---|---|---|---|
20 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 91.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 25.3 | |
RθJB | Junction-to-board thermal resistance | 42 | |
ψJT | Junction-to-top characterization parameter | 1 | |
ψJB | Junction-to-board characterization parameter | 41.5 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Resolution | 16 | 24 | 32 | Bits | |||
Data Format (PCM Mode) | |||||||
Audio data bit length | 16 | 24 | 32 | Bits | |||
fS(7) | Sampling frequency | 8 | 384 | kHz | |||
fSCK | System clock frequency | Clock multiples: 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072 | 50 | MHz | |||
Digital Input/Output for non-Q1 Consumer Grade Devices | |||||||
Logic family: 3.3 V LVCMOS compatible | |||||||
VIH | Input logic level | 0.7×DVDD | V | ||||
VIL | 0.3×DVDD | ||||||
IIH | Input logic current | VIN = VDD | 10 | µA | |||
IIL | VIN = 0 V | –10 | |||||
VOH | Output logic level | IOH = –4 mA | 0.8×DVDD | V | |||
VOL | IOL = 4 mA | 0.22×DVDD | |||||
Logic family 1.8 V LVCMOS compatible | |||||||
VIH | Input logic level | 0.7×DVDD | V | ||||
VIL | 0.3×DVDD | ||||||
IIH | Input logic current | VIN = VDD | 10 | µA | |||
IIL | VIN = 0 V | –10 | |||||
VOH | Output logic level | IOH = –2 mA | 0.8×DVDD | V | |||
VOL | IOL = 2 mA | 0.22×DVDD | |||||
Digital Input/Output for Q1 Automotive Grade Devices | |||||||
Logic family: 3.3 V LVCMOS compatible | |||||||
VIH | Input logic level | 0.7×DVDD | V | ||||
VIL | 0.3×DVDD | ||||||
IIH | Input logic current | VIN = VDD | 10 | µA | |||
IIL | VIN = 0 V | –10 | |||||
VOH | Output logic level | IOH = –4 mA | 0.8×DVDD | V | |||
VOL | IOL = 4 mA | 0.22×DVDD | |||||
Logic family 1.8 V LVCMOS compatible | |||||||
VIH | Input logic level | 0.7×DVDD | V | ||||
VIL | 0.3×DVDD | ||||||
IIH | Input logic current | VIN = VDD | 10 | µA | |||
IIL | VIN = 0 V | –10 | |||||
VOH | Output logic level | IOH = –2 mA | 0.8×DVDD | V | |||
VOL | IOL = 2 mA | 0.3×DVDD | |||||
Dynamic Performance (PCM Mode)(1)(2) | |||||||
THD+N at –1 dBFS(2) | fS = 48 kHz | PCM5102A | –93 | –83 | dB | ||
PCM5101A | –92 | –82 | |||||
PCM5100A | –90 | –80 | |||||
fS = 96 kHz and 192 kHz | PCM5102A | –93 | |||||
PCM5101A | –92 | ||||||
PCM5100A | –90 | ||||||
Dynamic range(2) | EIAJ, A-weighted, fS = 48 kHz | PCM5102A | 106 | 112 | |||
PCM5101A | 100 | 106 | |||||
PCM5100A | 95 | 100 | |||||
EIAJ, A-weighted, fS = 96 kHz and 192 kHz | PCM5102A | 112 | |||||
PCM5101A | 106 | ||||||
PCM5100A | 100 | ||||||
Signal-to-noise ratio(2) | EIAJ, A-weighted, fS = 48 kHz | PCM5102A | 112 | ||||
PCM5101A | 106 | ||||||
PCM5100A | 100 | ||||||
EIAJ, A-weighted, fS = 96 kHz and 192 kHz | PCM5102A | 112 | |||||
PCM5101A | 106 | ||||||
PCM5100A | 100 | ||||||
Signal to noise ratio with analog mute(2)(3) | EIAJ, A-weighted, fS = 48 kHz | 113 | 123 | ||||
EIAJ, A-weighted, fS = 96 kHz and 192 kHz | 123 | ||||||
Channel separation | fS = 48 kHz | PCM5102A | 100 | 109 | |||
PCM5101A | 95 | 103 | |||||
PCM5100A | 90 | 97 | |||||
fS = 96 kHz | PCM5102A | 109 | |||||
PCM5101A | 103 | ||||||
PCM5100A | 97 | ||||||
fS = 192 kHz | PCM5102A | 109 | |||||
PCM5101A | 103 | ||||||
PCM5100A | 97 | ||||||
Analog Output | |||||||
Output voltage | 2.1 | VRMS | |||||
Gain error | –6 | ±2 | 6 | % of FSR | |||
Gain error on Q1 Automotive Grade Devices | –7 | ±2 | 7 | % of FSR | |||
Gain mismatch, channel-to-channel | –6 | ±2 | 6 | % of FSR | |||
Gain mismatch, channel-to-channel on Q1 Devices | –6 | ±2 | 6 | % of FSR | |||
PCM5100/1 bipolar zero error | At bipolar zero | –5 | ±1 | 5 | mV | ||
PCM5102 Bipolar zero error | At bipolar zero | –2 | ±1 | 2 | mV | ||
Load impedance | 1 | kΩ | |||||
Filter Characteristics–1: Normal | |||||||
Pass band | 0.45fS | ||||||
Stop band | 0.55fS | ||||||
Stop band attenuation | –60 | dB | |||||
Pass-band ripple | ±0.02 | ||||||
Delay time | 20tS | s | |||||
Filter Characteristics–2: Low Latency | |||||||
Pass band | 0.47fS | ||||||
Stop band | 0.55fS | ||||||
Stop band attenuation | –52 | dB | |||||
Pass-band ripple | ±0.0001 | ||||||
Delay time | 3.5tS | s | |||||
Power Supply Requirements | |||||||
DVDD | Digital supply voltage | Target DVDD = 1.8 V | 1.65 | 1.8 | 1.95 | VDC | |
DVDD | Digital supply voltage | Target DVDD = 3.3 V | 3 | 3.3 | 3.6 | VDC | |
AVDD | Analog supply voltage | 3 | 3.3 | 3.6 | |||
CPVDD | Charge-pump supply voltage | 3 | 3.3 | 3.6 | |||
IDD | DVDD supply current at 1.8 V(4) | fS = 48 kHz | 7 | mA | |||
fS = 96 kHz | 8 | ||||||
fS = 192 kHz | 9 | ||||||
IDD | DVDD supply current at 1.8 V(5) | fS = 48 kHz | 7 | mA | |||
fS = 96 kHz | 8 | ||||||
fS = 192 kHz | 9 | ||||||
IDD | DVDD supply current at 1.8 V(6) | Standby | 0.3 | mA | |||
IDD | DVDD supply current at 3.3 V(4) | fS = 48 kHz | 7 | 12 | mA | ||
fS = 96 kHz | 8 | ||||||
fS = 192 kHz | 9 | ||||||
IDD | DVDD supply current at 3.3 V(5) | fS = 48 kHz | 8 | 13 | mA | ||
fS = 96 kHz | 9 | ||||||
fS = 192 kHz | 10 | ||||||
IDD | DVDD supply current at 3.3 V(6) | Standby | 0.5 | 0.8 | mA | ||
IDD | AVDD / CPVDD supply current(4) | fS = 48 kHz | 11 | 16 | mA | ||
fS = 96 kHz | 11 | ||||||
fS = 192 kHz | 11 | ||||||
IDD | AVDD / CPVDD supply current(5) | fS = 48 kHz | 22 | 32 | mA | ||
fS = 96 kHz | 22 | ||||||
fS = 192 kHz | 22 | ||||||
IDD | AVDD / CPVDD supply current(6) | fS = n/a | 0.2 | 0.4 | mA | ||
Power dissipation, DVDD = 1.8 V(4) | fS = 48 kHz | 49 | 185 | mW | |||
fS = 96 kHz | 51 | ||||||
fS = 192 kHz | 53 | ||||||
Power dissipation, DVDD = 1.8 V(5) | fS = 48 kHz | 85 | 187 | mW | |||
fS = 96 kHz | 87 | ||||||
fS = 192 kHz | 89 | ||||||
Power dissipation, DVDD = 1.8 V(6) | fS = n/a (Power Down Mode) | 1 | mW | ||||
Power dissipation, DVDD = 3.3 V(4) | fS = 48 kHz | 60 | 92.4 | mW | |||
fS = 96 kHz | 63 | ||||||
fS = 192 kHz | 66 | ||||||
Power dissipation, DVDD = 3.3 V(5) | fS = 48 kHz | 99 | 148.5 | mW | |||
fS = 96 kHz | 102 | ||||||
fS = 192 kHz | 106 | ||||||
Power dissipation, DVDD = 3.3 V(6) | fS = n/a (Power Down Mode) | 2 | 4 | mW |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
tSCY | System clock pulse cycle time | 20 | 1000 | ns | ||
tSCKH | System clock pulse width, High | DVDD = 1.8 V | 8 | ns | ||
DVDD = 3.3 V | 9 | |||||
tSCKL | System clock pulse width, Low | DVDD = 1.8 V | 8 | ns | ||
DVDD = 3.3 V | 9 |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
tr | Rise time | 20 | ns | ||
tf | Fall time | 20 | ns |