The PCM514x devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM514x uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.
Members of the PCM514x family integrate a fully programmable miniDSP core, allowing developers to integrate filters, dynamic range controls, custom interpolators, and other differentiating features to their products.
The PCM514x provides 2.1-VRMS ground centered outputs, allowing designers to eliminate DC-blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.
The integrated line driver surpasses all other charge-pump-based line drivers by supporting loads down to 1 kΩ, allowing the PCM514x to drive up to 10 products in parallel, such as LCD TV, DVDR, and AV receivers.
The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.
DEVICE NAME | PACKAGE | BODY SIZE (NOM) |
---|---|---|
PCM5141 | TSSOP (28) | 9.70 mm × 4.40 mm |
PCM5142 |
.
Changes from A Revision (September 2012) to B Revision
PART NUMBER | DYNAMIC RANGE | SNR | THD |
---|---|---|---|
PCM5142A | 112 dB | 112 dB | –93 dB |
PCM5141A | 106 dB | 106 dB | –92 dB |
PARAMETER | PCM5142 / PCM5141 |
---|---|
SNR | 112 / 106 dB |
Dynamic range | 112 /106 dB |
THD+N at –1 dBFS | –93/ –92 dB |
Full-scale single-ended output | 2.1 VRMS (GND center) |
Normal 8× oversampling digital filter latency | 20tS |
Low latency 8× oversampling digital filter latency | 3.5tS |
Sampling frequency | 8 kHz to 384 kHz |
System clock multiples (fSCK): 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072 | Up to 50 MHz |
ATT PIN CONDITION (ATT2 : ATT1 : ATT0) | GAIN AND ATTENUATION LEVEL |
---|---|
( 0 0 0 ) | 0 dB |
( 0 0 1 ) | 3 dB |
( 0 1 0 ) | 6 dB |
( 0 1 1 ) | 9 dB |
( 1 0 0 ) | 12 dB |
( 1 0 1 ) | 15 dB |
( 1 1 0 ) | –6 dB |
( 1 1 1 ) | –3 dB |
PIN | I/O | DESCRIPTION | |||||
---|---|---|---|---|---|---|---|
NAME | MODE, NO. | ||||||
I2C | SPI | HW | |||||
CPVDD | 1 | 1 | 1 | - | Charge pump power supply, 3.3 V | ||
CAPP | 2 | 2 | 2 | O | Charge pump flying capacitor terminal for positive rail | ||
CPGND | 3 | 3 | 3 | - | Charge pump ground | ||
CAPM | 4 | 4 | 4 | O | Charge pump flying capacitor terminal for negative rail | ||
VNEG | 5 | 5 | 5 | O | Negative charge pump rail terminal for decoupling, –3.3 V | ||
OUTL | 6 | 6 | 6 | O | Analog output from DAC left channel | ||
OUTR | 7 | 7 | 7 | O | Analog output from DAC right channel | ||
AVDD | 8 | 8 | 8 | - | Analog power supply, 3.3 V | ||
AGND | 9 | 9 | 9 | - | Analog ground | ||
VCOM | 10 | 10 | – | O | I2C, SPI | VCOM output (optional mode selected by register; default setting is VREF mode.) When in VREF mode (default), this pin ties to GND. When in VCOM mode, decoupling capacitor to GND is required. | |
DEMP | – | – | 10 | I | HW | DEMP: De-emphasis control for 44.1-kHz sampling rate: Off (Low) / On (High) | |
SDA | 11 | – | – | I/O | I2C | Data for I2C(1)(2) | |
MOSI | – | 11 | – | I | SPI | Input data for SPI(2) | |
ATT2 | – | – | 11 | HW | Digital gain and attenuation control pin | ||
SCL | 12 | – | – | I | I2C | Input clock for I2C(2) | |
MC | – | 12 | – | SPI | Input clock for SPI(2) | ||
ATT1 | – | – | 12 | HW | Digital gain and attenuation control pin | ||
GPIO5 | 13 | 13 | – | I/O | I2C, SPI | General purpose digital input and output port (3) | |
ATT0 | – | – | 13 | HW | Digital gain and attenuation control pin | ||
GPIO4 | 14 | 14 | – | I/O | I2C, SPI | General purpose digital input and output port (3) | |
MAST | – | – | 14 | HW | I2S Master clock select pin : Master (High) BCK/LRCK outputs, Slave (Low) BCK/LRCK inputs | ||
GPIO3 | 15 | 15 | – | I/O | I2C, SPI | General purpose digital input and output port (3) | |
AGNS | – | – | 15 | HW | Analog gain selector : 0-dB 2-VRMS output (Low), –6-dB 1-VRMS output (High) | ||
ADR2 | 16 | – | – | I/O | I2C | 2nd LSB address select bit for I2C | |
GPIO2 | – | 16 | – | SPI | General purpose digital input and output port | ||
DOUT | – | – | 16 | O | HW | General Purpose Output (Low level) | |
MODE1 | 17 | 17 | 17 | I | Mode control selection pin (2)
MODE1 = Low, MODE2 = Low : Hardwired mode MODE1 = Low, MODE2 = High: I2C mode MODE1 = High: SPI mode |
||
MODE2 | 18 | – | 18 | I2C, HW | MODE2 | ||
MS | – | 18 | – | I | SPI | MS pin (chip select for SPI) | |
GPIO6 | 19 | 19 | – | I/O | I2C, SPI | General purpose digital input and output port | |
FLT | – | – | 19 | I | HW | Filter select : Normal latency (Low) / Low latency (High) | |
SCK | 20 | 20 | 20 | I | System clock input(2) | ||
BCK | 21 | 21 | 21 | I/O | Audio data bit clock input (slave) or output (master)(2) | ||
DIN | 22 | 22 | 22 | I | Audio data input(2) | ||
LRCK | 23 | 23 | 23 | I/O | Audio data word clock input (slave) or output (master)(2) | ||
ADR1 | 24 | – | – | I/O | I2C | LSB address select bit for I2C | |
MISO (GPIO1) | – | 24 | – | SPI | Primary output data for SPI readback. Secondary; general purpose digital input/output port controlled by register | ||
FMT | – | – | 24 | HW | Audio format selection : I2S (Low) / Left justified (High) | ||
XSMT | 25 | 25 | 25 | I | Soft mute control Soft mute(2) (Low) / soft un-mute (High) | ||
LDOO | 26 | 26 | 26 | - | Internal logic supply rail terminal for decoupling, 1.8 V | ||
DGND | 27 | 27 | 27 | - | Digital ground | ||
DVDD | 28 | 28 | 28 | - | Digital power supply, 3.3 V or 1.8 V |