The PCM5242 is a monolithic CMOS integrated circuit that includes a stereo digital-to-analog converter and additional support circuitry in a small QFN package. The PCM5242 uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.
The PCM5242 integrates a fully programmable miniDSP core, allowing developers to integrate filters, dynamic range controls, custom interpolators and other differentiating features to their products.
The PCM5242 provides 4.2VRMS ground-centered differential outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single supply line drivers.
The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.
PART NAME | PACKAGE | BODY SIZE (NOM) |
---|---|---|
PCM5242 | VQFN (32) | 5.00mm × 5.00mm |
Parameter | PCM5242 |
SNR | 114dB |
Dynamic Range | 114dB |
THD+N at - 1dBFS | –94dB |
Full Scale Differential Output | 4.2VRMS (GND center) |
Normal 8× Oversampling Digital Filter Latency: 20tS | |
Low Latency 8× Oversampling Digital Filter Latency: 3.5tS | |
Sampling Frequency | 8kHz to 384kHz |
System Clock Multiples (fSCK): 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072; up to 50 MHz |
Changes from Initial Revision (July 2014) to A Revision
The PCM5242 supports control from I2C, SPI and Hardware Modes (referred to as HW mode). Selection of modes is done using Mode1 and Mode2 pins. (See Table 1)
SPI Mode is selected by pulling MODE1 to DVDD.
I2C Mode is selected by pulling MODE1 to DGND and Mode2 to DVDD.
Hardware Control Mode is selected by pulling both MODE1 and MODE2 pins to DGND.
PIN | I/O | DESCRIPTION | |||||
---|---|---|---|---|---|---|---|
MODE, NAME | PIN | ||||||
I2C | SPI | HW | |||||
XSMT | 1 | I | Soft mute control(2) Soft mute (Low) / soft un-mute (High) | ||||
LDOO | 2 | - | Internal logic supply rail pin for decoupling, 1.8V | ||||
DGND | 3 | - | Digital ground | ||||
DVDD | 4 | - | Digital power supply, 3.3V or 1.8V | ||||
CPVDD | 5 | - | Charge pump power supply, 3.3V | ||||
CAPP | 6 | O | Charge pump flying capacitor pin for positive rail | ||||
CPGND | 7 | - | Charge pump ground | ||||
CAPM | 8 | O | Charge pump flying capacitor pin for negative rail | ||||
VNEG | 9 | O | Negative charge pump rail pin for decoupling, -3.3V | ||||
OUTLP | 10 | Positive Differential Analog output from DAC left channel | |||||
OUTLN | 11 | Negative Differential Analog output from DAC left channel | |||||
OUTRN | 12 | Negative Differential Analog output from DAC right channel | |||||
OUTRP | 13 | Positive Differential Analog output from DAC right channel. | |||||
AVDD | 14 | - | Analog power supply, 3.3V | ||||
AGND | 15 | - | Analog ground | ||||
VCOM | 16 | O | I2C, SPI | VCOM output (Optional mode selected by register; default setting is VREF mode.) When in VREF mode (default), this pin ties to GND. When in VCOM mode, decoupling capacitor to GND is required. | |||
DEMP | I | HW | DEMP: De-emphasis control for 44.1kHz sampling rate: Off (Low) / On (High) | ||||
SDA | 17 | I/O | I2C | Data for I2C(1)(2) | |||
MOSI | I | SPI | Input data for SPI(2) | ||||
ATT2 | HW | Digital gain and attenuation control pin | |||||
SCL | 18 | I | I2C | Input clock for I2C(2) | |||
MC | SPI | Input clock for SPI(2) | |||||
ATT1 | HW | Digital gain and attenuation control pin | |||||
GPIO5 | 19 | I/O | I2C, SPI | General purpose digital input and output port (3) | |||
ATT0 | HW | Digital gain and attenuation control pin | |||||
GPIO4 | 20 | I/O | I2C, SPI | General purpose digital input and output port (3) | |||
MAST | HW | I2S Master clock select pin : Master (High) BCK/LRCK outputs, Slave (Low) BCK/LRCK inputs | |||||
GPIO3 | 21 | I/O | I2C, SPI | General purpose digital input and output port (3) | |||
AGNS | HW | Analog gain selector : 0dB 2VRMS output (Low), -6dB 1VRMS output (High) | |||||
ADR2 | 22 | I/O | I2C | 2nd LSB address select bit for I2C(3) | |||
GPIO2 | SPI | General purpose digital input and output port (3) | |||||
GPO | O | HW | General Purpose Output (Low level) | ||||
MODE1 | 23 | I | Mode control selection pin(2) | ||||
MODE1 = Low, MODE2 = Low : Hardwired mode | |||||||
MODE1 = Low, MODE2 = High: I2C mode | |||||||
MODE1 = High: SPI mode | |||||||
MODE2 | MODE2 | 24 | I2C, HW | MODE2 (See definition in Mode 1 description) | |||
MS | I | SPI | MS pin (chip select for SPI) | ||||
GPIO6 | 25 | I/O | I2C, SPI | General purpose digital input and output port | |||
FLT | I | HW | Filter select : Normal latency (Low) / Low latency (High) | ||||
SCK | 26 | I | System clock input(2) | ||||
BCK | 27 | I/O | Audio data bit clock input (slave) or output (master)(2) | ||||
DIN | 28 | I | Audio data input(2) | ||||
NC | 29 | - | No connect | ||||
30 | - | ||||||
LRCK | 31 | I/O | Audio data word clock input (slave) or output (master)(2) | ||||
ADR1 | 32 | I/O | I2C | LSB address select bit for I2C | |||
MISO (GPIO1) | SPI | Primary output data for SPI readback. Secondary; general purpose digital input/output port controlled by register | |||||
FMT | HW | Audio format selection : I2S (Low) / Left justified (High) |
ATT PIN CONDITION (ATT2 : ATT1 : ATT0) |
GAIN AND ATTENUATION LEVEL |
( 0 0 0 ) | 0 dB |
( 0 0 1 ) | + 3 dB |
( 0 1 0 ) | + 6 dB |
( 0 1 1 ) | + 9 dB |
( 1 0 0 ) | + 12 dB |
( 1 0 1 ) | + 15 dB |
( 1 1 0 ) | - 6 dB |
( 1 1 1 ) | - 3 dB |