The TI Dynamic NFC/RFID Interface Transponder RF430CL331H is an NFC Tag Type 4 device that combines a contactless NFC/RFID interface and a wired I2C interface to connect the device to a host. The NDEF message can be written and read from the integrated I2C serial communication interface and can also be accessed and updated over a contactless interface using the integrated ISO/IEC 14443 Type B compliant RF interface that supports up to 848 kbps.
The device requests responses to NFC Type 4 commands on demand from the host controller and stores only a portion of the NDEF message in its buffer at any one time. This allows NDEF message size to be limited only by the memory capacity of the host controller and specification limitations.
Support of read caching, prefetching, and write automatic acknowledgment features allows for greater data throughput.
This device enables NFC connection handover for an alternative carrier like Bluetooth®, Bluetooth® low energy (BLE), or Wi-Fi as an easy and intuitive pairing process or authentication process with only a tap.
As a general NFC interface, the RF430CL331H enables end equipment to communicate with the fast-growing infrastructure of NFC-enabled smart phones, tablets, and notebooks.
PART NUMBER | PACKAGE | BODY SIZE (2) |
---|---|---|
RF430CL331HIPW | TSSOP (14) | 5 mm × 4.4 mm |
RF430CL331HRGT | VQFN (16) | 3 mm × 3 mm |
Figure 3-1 shows the pinout for the 14-pin PW package.
Figure 3-2 shows the pinout for the 16-pin RGT package.
PIN NUMBER | SIGNAL NAME | SIGNAL TYPE (1) | BUFFER TYPE (2) | POWER SOURCE | RESET STATE (3) | |
---|---|---|---|---|---|---|
PW | RGT | |||||
1 | 15 | VCC | PWR | Power | VCC | N/A |
2 | 1 | ANT1 | RF | Analog | – | N/A |
3 | 2 | ANT2 | RF | Analog | – | N/A |
4 | 3 | RST | I | LVCMOS | VCC | PU |
5 | 4 | E0 | I | LVCMOS | VCC | OFF |
6 | 5 | E1 | I | LVCMOS | VCC | OFF |
7 | 6 | E2 | I | LVCMOS | VCC | OFF |
8 | 7 | INTO | O | LVCMOS | VCC | OFF |
9 | 8 | I2C_READY | O | LVCMOS | VCC | DRIVE1 |
10 | 9 | I2C_SIGNAL | O | LVCMOS | VCC | DRIVE1 |
11 | 10 | SCL | I/O | LVCMOS | VCC | OFF |
12 | 11 | SDA | I/O | LVCMOS | VCC | OFF |
13 | 12 | VCORE | PWR | Power | VCC | N/A |
14 | 13 | VSS | PWR | Power | VCC | N/A |
– | 14 | NC | – | – | – | – |
– | 16 | NC | – | – | – | – |
Table 3-2 describes the signals.
FUNCTION | SIGNAL NAME | PIN NUMBER | I/O (1) | DESCRIPTION | |
---|---|---|---|---|---|
PW | RGT | ||||
Power | VCC | 1 | 15 | PWR | 3.3-V power supply |
VCORE | 13 | 12 | PWR | Regulated core supply voltage | |
VSS | 14 | 13 | PWR | Ground supply | |
RF | ANT1 | 2 | 1 | RF | Antenna input 1 |
ANT2 | 3 | 2 | RF | Antenna input 2 | |
Serial communication | E0 | 5 | 4 | I | I2C address select 0 |
E1 | 6 | 5 | I | I2C address select 1 | |
E2 | 7 | 6 | I | I2C address select 2 | |
I2C_READY | 9 | 8 | O | High indicates that I2C communication can be started. Low indicates that I2C communication must not be started. | |
I2C_SIGNAL | 10 | 9 | O | Low indicates that a wait time extension command is automatically being sent. I2C communication does not have to be stopped. | |
SCL | 11 | 10 | I/O | I2C clock | |
SDA | 12 | 11 | I/O | I2C data | |
System | INTO | 8 | 7 | O | Interrupt output |
RST | 4 | 3 | I | Reset input (active low) (2) | |
No connect | NC | – | 14 16 |
– | Leave open, no connection |
None of the pins on this device are multiplexed.
BUFFER TYPE (STANDARD) | NOMINAL VOLTAGE | HYSTERESIS | PU OR PD | NOMINAL PU OR PD STRENGTH (µA) | OUTPUT DRIVE STRENGTH (mA) | OTHER CHARACTERISTICS |
---|---|---|---|---|---|---|
LVCMOS | 3.3 V | Y | N/A | See Section 4.6, Electrical Characteristics, Digital Inputs | See Section 4.7, Electrical Characteristics, Digital Outputs | |
Analog, RF | 3.3 V | N | N/A | N/A | N/A | See analog modules in Section 4, Specifications, for details |
Power | 3.3 V | Y with SVS on | N/A | N/A | N/A |
Leave no connect (NC) pins unconnected.
Leave unused outputs unconnected.
Drive or pull unused inputs high or low.