SLAS834C November 2012 – December 2014 RF430FRL152H , RF430FRL153H , RF430FRL154H
PRODUCTION DATA.
The RF430FRL15xH device is a 13.56-MHz transponder chip with a programmable 16-bit MSP430™ low-power microcontroller. The device features embedded universal FRAM nonvolatile memory for storage of program code or user data such as calibration and measurement data. The RF430FRL15xH supports communication, parameter setting, and configuration through the ISO/IEC 15693, ISO/IEC 18000-3 compliant RFID interface and the SPI or I2C interface. Sensor measurements are supported by the internal temperature sensor and the onboard 14-bit sigma-delta analog-to-digital converter (ADC), and digital sensors can be connected through SPI or I2C.
The RF430FRL15xH device is optimized for operation in fully passive (battery-less) or single-cell battery-powered (semi-active) mode to achieve extended battery life in portable and wireless sensing applications. FRAM is a nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and reliability of flash, all at lower total power consumption.
PART NUMBER | PACKAGE | BODY SIZE(2) |
---|---|---|
RF430FRL152H | VQFN (24) | 4 mm x 4 mm |
RF430FRL153H | VQFN (24) | 4 mm x 4 mm |
RF430FRL154H | VQFN (24) | 4 mm x 4 mm |
Figure 1-1 shows the block diagram of the RF430FRL15xH device.
Changes from November 13, 2014 to December 8, 2014
Table 3-1 summarizes the available family members.
Device | FRAM (KB) |
SRAM (KB) |
Timer | 13.56-MHz ISO/IEC 15693 Front End | eUSCI_B | SD14 |
---|---|---|---|---|---|---|
RF430FRL152H | 2 | 4 | Yes | Yes | Yes | Yes |
RF430FRL153H | 2 | 4 | Yes | Yes | No | Yes |
RF430FRL154H | 2 | 4 | Yes | Yes | Yes | No |
Figure 4-1 shows the pin assignments on the 24-pin RGE package.
Table 4-1 describes the signals.
TERMINAL | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ANT1 | 1 | I | Antenna input 1 |
ANT2 | 2 | I | Antenna input 2 |
VDDSW | 3 | Switched supply voltage | |
VDDB | 4 | Battery supply voltage | |
CP1 | 5 | Charge pump flying cap terminal 1 | |
CP2 | 6 | Charge pump flying cap terminal 2 | |
VDD2X | 7 | Voltage doubler output | |
P1.3 SPI_STE TA0.2 ACLK TA0CLK |
8 | I/O |
General-purpose digital I/O SPI slave transmit enable Timer_A TA0 OUT2 output ACLK output (divided by 1, 2, 4, 8, 16, or 32) Timer_A TA0 clock signal TA0CLK input |
P1.2 SPI_CLK MCLK TA0.0 |
9 | I/O |
General-purpose digital I/O SPI clock MCLK output Timer_A TA0 OUT0 output |
RST/NMI | 10 | I |
Reset input active low Non-maskable interrupt input |
P1.1 SPI_SOMI SCL ACLK TA0.2 CCI0.0 |
11 | I/O |
General-purpose digital I/O SPI slave out master in I2C clock ACLK output (divided by 1, 2, 4, or 8 ) Timer_A TA0 OUT2 output Timer_A TA0 CCR0 capture: CCI0B input, compare |
P1.0 SPI_SIMO SDA SMCLK TA0.1 CCI0.0 |
12 | I/O |
General-purpose digital I/O SPI slave in master out I2C data SMCLK output Timer0_A3 OUT1 output Timer_A TA0 CCR0 capture: CCI0A input, compare |
ADC0 | 13 | I | ADC input pin 0 |
TST2 | 14 | Internal; connect to GND | |
SVSS | 15 | Sensor reference potential | |
TST1 | 16 | Internal; connect to GND | |
ADC1 / TEMP1 | 17 | ADC input pin 1 / Resistive bias pin 1 | |
ADC2 / TEMP2 | 18 | ADC input pin 2 / Resistive bias pin 2 | |
TMS P1.7 TA0.1 TA0.0 CCI0.2 |
19 | I/O |
JTAG test mode select General-purpose digital I/O Timer_A TA0 OUT1 output Timer_A TA0 OUT0 output Timer_A TA0 CCR2 capture: CCI2B input, compare |
TDO P1.6 TA0.0 TA0.2 CCI0.2 |
20 | I/O |
JTAG test data output General-purpose digital I/O Timer_A TA0 OUT0 output Timer_A TA0 OUT2 output Timer_A TA0 CCR2 capture: CCI2A input, compare |
TDI P1.5 TA0.2 MCLK CCI0.1 |
21 | I/O |
JTAG test data input General-purpose digital I/O Timer_A TA0 OUT2 output MCLK output Timer_A TA0 CCR1 capture: CCI1B input, compare |
TCK P1.4 TA0.1 SMCLK CCI0.1 CLKIN |
22 | I/O |
JTAG test clock General-purpose digital I/O Timer_A TA0 OUT1 output SMCLK output Timer_A TA0 CCR1 capture: CCI1A input, compare External clock input pin |
VDDH | 23 | O | Rectified voltage from RF-AFE |
VDDD | 24 | Digital supply voltage | |
VSS | Pad | Ground reference, bonded to exposed pad(2) |
The GPIO port pins are multiplexed with other functions including analog peripherals and serial communication modules. The pin functions are selected by a combination of register values and device modes. For schematics of the port pins and details of the multiplexing for each, refer to Section 6.7.
The correct termination of all unused pins is listed in Table 4-2.
Pin | Potential | Comment |
---|---|---|
TDI/TMS/TCK | Open | When used for JTAG function |
RST/NMI | VCC or VSS | 10-nF capacitor to GND/VSS |
Px.0 to Px.7 | Open | Set to port function, output direction |
TDO | Open | Convention: leave TDO terminal as JTAG function |
MIN | MAX | UNIT | |
---|---|---|---|
Voltage applied at VDDB referenced to VSS (VAMR) | -0.3 | 1.65 | V |
Voltage applied at VANT referenced to VSS (VAMR) | -0.3 | 3.6 | V |
Voltage applied to any pin (references to VSS) | -0.3 | VDDB + 0.3 | V |
Diode current at any device pin(2) | ±2 | mA | |
Current derating factor when I/O ports are switched in parallel electrically and logically(3) | 0.9 | ||
Storage temperature range, Tstg(4)(5)(6) | -40 | 125 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
VESD | Electrostatic discharge (ESD) performance | Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1)(2) | ±2000 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDDB | Supply voltage during program execution | 1.45 | 1.65 | V | |
VSS | Supply voltage (GND reference) | 0 | V | ||
TA | Operating free-air temperature | 0 | 70 | °C | |
CVDDB | Capacitor on VDDB(1) | 100 | nF | ||
CVDDSW | Capacitor on VDDSW(1) | 2.2 | µF | ||
CFLY | Charge pump capacitor between CP1 and CP2. Recommended ratio between CFLY and CVDD2X is ≥ 1:10. (1) |
10 | nF | ||
CVDD2X | Capacitor on VDD2x. Recommended ratio between CFLY and CVDD2X is ≥ 1:10.(1) |
100 | nF | ||
CVDDD | Capacitor on VDDD(1) | 1 | µF | ||
CSVSS | Capacitor between SVSS and VSS(1) | 1 | µF | ||
fSYSTEM | System frequency(2)(3) | 2 | MHz | ||
fCLKIN | External clock input frequency | 32 | kHz |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fc | Carrier frequency | 13.56 | MHz | ||
VANT_peak | Antenna input voltage | 3.6 | V | ||
Z | Impedance of LC circuit | 6.5 | 15.5 | kΩ | |
LRES | Coil inductance | 2.66 | µH | ||
CRES | Resonance capacitance | 51.8 – CIN(1) | pF | ||
QT | Tank quality factor | 30 |
PARAMETER | EXECUTION MEMORY |
VDDB | Frequency (fMCLK = fSMCLK) | UNIT | |||
---|---|---|---|---|---|---|---|
1 MHz | 2 MHz | ||||||
TYP | MAX | TYP | MAX | ||||
IAM, FRAM(2) | FRAM | 1.5 V | 330 | 420 | 480 | 580 | µA |
IAM, RAM(2) | RAM | 1.5 V | 220 | 300 | 250 | 320 | µA |
IAM, ROM(2) | ROM | 1.5 V | 220 | 300 | 230 | 300 | µA |
PARAMETER | VDDB | 0ºC | 20ºC | 45ºC | 70ºC | UNIT | |||||
---|---|---|---|---|---|---|---|---|---|---|---|
TYP | MAX | TYP | MAX | TYP | MAX | TYP | MAX | ||||
ILPM0(2) | fMCLK = off, fSMCLK = 1 MHz, fACLK = 32 kHz, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 |
1.5 V | 170 | 230 | 190 | 210 | 260 | 340 | µA | ||
ILPM3(3) | fMCLK = fSMCLK = off, fACLK = 16 kHz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 |
1.5 V | 12 | 20 | 13 | 16 | 25 | 65 | µA | ||
ILPM4(4) | fMCLK = fSMCLK = fACLK = 0 Hz CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 |
1.5 V | 11 | 16 | 12 | 15 | 24 | 60 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VOH | High-level output voltage | VDDB = 1.5 V, IOH = -400 µA(1) for port P1 | VDDB – 0.15 | V | ||
VOL | Low-level output voltage | VDDB = 1.5 V, IOL = 400 µA(2) for port P1 | 0.15 | V | ||
VIH | High-level input voltage | VDDB = 1.5 V | 0.7 × VDDB | V | ||
VIL | Low-level input voltage | VDDB = 1.5 V | 0.3 × VDDB | V | ||
IOH | High-level output current | VDDB = 1.45 V to 1.65 V for port P1 | -400 | µA | ||
IOL | Low-level output current | VDDB = 1.45 V to 1.65 V for port P1 | 400 | µA | ||
ILKG | High-impedance leakage current | VDDB = 1.45 V to 1.65 V | -100 | 100 | nA | |
tINT | External interrupt timing(3) | P1.x, VDDB = 1.45 V to 1.65 V | 200 | ns | ||
RPULL | Pullup or pulldown resistor | VDDB=1.5 V, For pullup: VIN = VSS, For pulldown: VIN = VDDB for port P1 |
30 | 35 | 40 | kΩ |
RRST | Pullup on RST/NMI | 30 | 35 | 40 | kΩ | |
REXT | External pullup resistor on RST terminal (optional) | 47 | kΩ | |||
CEXT | External capacitor on RST terminal | 10 | nF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
fHFOSC | ±20% | 3.04 | 3.8 | 4.56 | MHz |
Duty cycle | 45% | 50% | 55% | ||
tSTART | 1 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
fLFO | trimmed ±5% | 243 | 256 | 269 | kHz |
Duty cycle | 45% | 50% | 55% | ||
tSTART | 11 | µs |
PARAMETER | TEST CONDITIONS | VDDB | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tWAKE-UP LPM0 | Wake-up time from LPM0 to active mode(1) | 1.5 V | 3.2 | 6 | µs | ||
tWAKE-UP LPM34 | Wake-up time from LPM3 or LPM4 to active mode(1) | 1.5 V | 160 | 260 | µs | ||
tWAKE-UP RESET | Wake-up time from RST to active mode.(2) | VDDB stable | 1.5 V | 210 | 310 | µs |
PARAMETER | TEST CONDITIONS | VDDB | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fTA | Timer_A input clock frequency | Internal: SMCLK, ACLK External: TACLK Duty cycle = 50% ± 10% |
1.5 V | 4 | MHz | ||
tTA,cap | Timer_A capture timing | All capture inputs, Minimum pulse duration required for capture | 1.5 V | 20 | ns |
PARAMETER | CONDITIONS | VDDB | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK, ACLK Duty cycle = 50% ± 10% |
1.5 V | fSYSTEM | MHz |
PARAMETER | TEST CONDITIONS | VDDB | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tSTE,LEAD | STE lead time, STE active to clock | UCSTEM = 0, UCMODEx = 01 or 10 |
1.5 V | 1 | UCxCLK cycles |
||
UCSTEM = 1, UCMODEx = 01 or 10 |
1.5 V | 1 | |||||
tSTE,LAG | STE lag time, Last clock to STE inactive | UCSTEM = 0, UCMODEx = 01 or 10 |
1.5 V | 1 | UCxCLK cycles |
||
UCSTEM = 1, UCMODEx = 01 or 10 |
1.5 V | 1 | |||||
tSTE,ACC | STE access time, STE active to SIMO data out | UCSTEM = 0, UCMODEx = 01 or 10 |
1.5 V | 55 | ns | ||
UCSTEM = 1, UCMODEx = 01 or 10 |
1.5 V | 35 | |||||
tSTE,DIS | STE disable time, STE inactive to SIMO high impedance | UCSTEM = 0, UCMODEx = 01 or 10 |
1.5 V | 40 | ns | ||
UCSTEM = 1, UCMODEx = 01 or 10 |
1.5 V | 30 | |||||
tSU,MI | SOMI input data setup time | 1.5 V | 35 | ns | |||
tHD,MI | SOMI input data hold time | 1.5 V | 0 | ns | |||
tVALID,MO | SIMO output data valid time(2) | UCLK edge to SIMO valid, CL = 20 pF |
1.5 V | 30 | ns | ||
tHD,MO | SIMO output data hold time(3) | CL = 20 pF | 1.5 V | 0 | ns |
PARAMETER | TEST CONDITIONS | VDDB | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tSTE,LEAD | STE lead time, STE active to clock | 1.5 V | 7 | ns | |||
tSTE,LAG | STE lag time, Last clock to STE inactive | 1.5 V | 0 | ns | |||
tSTE,ACC | STE access time, STE active to SOMI data out | 1.5 V | 65 | ns | |||
tSTE,DIS | STE disable time, STE inactive to SOMI high impedance | 1.5 V | 40 | ns | |||
tSU,SI | SIMO input data setup time | 1.5 V | 2 | ns | |||
tHD,SI | SIMO input data hold time | 1.5 V | 5 | ns | |||
tVALID,SO | SOMI output data valid time(2) | UCLK edge to SOMI valid, CL = 20 pF |
1.5 V | 30 | ns | ||
tHD,SO | SOMI output data hold time(3) | CL = 20 pF | 1.5 V | 4 | ns |
PARAMETER | TEST CONDITIONS | VDDB | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% |
fSYSTEM | MHz | |||
fSCL | SCL clock frequency | 1.5 V | 0 | 400 | kHz | ||
tHD,STA | Hold time (repeated) START | fSCL = 100 kHz | 1.5 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tSU,STA | Setup time for a repeated START | fSCL = 100 kHz | 1.5 V | 4.7 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tHD,DAT | Data hold time | 1.5 V | 0 | ns | |||
tSU,DAT | Data setup time | 1.5 V | 250 | ns | |||
tSU,STO | Setup time for STOP | fSCL = 100 kHz | 1.5 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tSP | Pulse duration of spikes suppressed by input filter | UCGLITx = 0 | 1.5 V | 50 | 600 | ns | |
UCGLITx = 1 | 25 | 300 | ns | ||||
UCGLITx = 2 | 12.5 | 150 | ns | ||||
UCGLITx = 3 | 6.25 | 75 | ns | ||||
tTIMEOUT | Clock low time-out | UCCLTOx = 1 | 1.5 V | 27 | ms | ||
UCCLTOx = 2 | 30 | ms | |||||
UCCLTOx = 3 | 33 | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tWRITE | Word or byte write time | 125 | ns | |||
Read/write endurance | 1015 | cycles | ||||
tRetention | Data retention duration | TJ = 25°C | 10 | years |
PARAMETER | VDDB | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fTCK | TCK input frequency, 4-wire JTAG(1) | 1.5 V | 0 | 4 | MHz |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VTH+ | Positive going switching threshold VTH+ = VDDB-VDDR |
35 | 60 | mV | ||
VTH- | Negative going switching threshold VTH- = VDDB-VDDR |
-60 | -35 | mV | ||
VHYST | Switching voltage hysteresis VHYST = VTH+-VTH- |
30 | 70 | 110 | mV | |
IBASVBAT | VDDB input leakage current | VDDB = 1.65 V, Battery switch open | 20 | nA | ||
VDROP | VDROP= VDDB - VDDSW(1) | 50 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VREF | Output voltage | VDDSW = 1.4 V to 1.65 V | 892 | 908 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VDD2X | Output voltage | VDDSW = 1.4 V, IDD2X = 1 µA, cont = 0 | 2 × VDDSW – 74mV | mV | ||
VDD2X | Output voltage | VDDSW = 1.4 V, IDD2X = 100 µA, cont = 1 | 2 × VDDSW – 104mV | mV |
PARAMETER | VDDSW | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VDDBTH+ | Positive threshold | 1.5 V | 1.45 | V | ||
VDDBTH- | Negative threshold | 1.5 V | 1.40 | V | ||
VDDSWTH+ | Positive threshold | 1.40 | V | |||
VDDSWTH- | Negative threshold | 1.35 | V | |||
VDDDTH+ | Positive threshold | 1.5 V | 1.00 | V | ||
VDDDTH- | Negative threshold | 1.5 V | 0.90 | V | ||
VDD2XTH+ | Positive threshold | 1.5 V | 2.70 | V | ||
VDD2XTH- | Negative threshold | 1.5 V | 2.475 |
V |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
fM | Modulator clock frequency | Internal LF oscillator as clock source for SD14 module | 2 | kHz | ||
RES | Resolution | 8 | 14 | Bit | ||
OSR | Oversampling ratio | 40 | 2048 | |||
B | Bandwidth of input signal | 1 | Hz | |||
VI | Input voltage range | VI = VADCx - VSVSS | 0 | VREF | mV | |
Voffset | Offset error | Complete signal chain | -0.75 | 0.75 | % of FSR(2) | |
VGErr | Gain error(1) | complete signal chain | -2% | 2% | ||
∆EG/∆T | Gain error temperature coefficient. (3) | complete signal chain | 100 | ppm/K | ||
EUnadjusted | Total unadjusted error | -2 | 2 | % of FSR(2) | ||
tStart | Startup time | 20 | CLK cycles |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VSVSS | Output voltage | ISVSS = -5uA .. 0uA | 80 | 125 | 165 | mV |
tSettling | Settling time after switching SVSS on (95% of final voltage) | Switch from VIRTGND = 1 to VIRTGND = 0 | 400 | 1000 | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IOUT,TH | Output current | VOUT = 0 to 0.7 V | 2.0 | 2.4 | 3.0 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tc | Temperature coefficient | 35.7 | LSB/K |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VDDH | Antenna rectified voltage | IDDH = 100 µA | 1.8 | 2 | 3.6 | V |
CIN | Input capacitance | 2 V RMS | 31.5 | 35 | 38.5 | pF |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
DR100 | Input signal data rate 100% downlink modulation, 100% ASK, ISO/IEC 15693 | 6 | 26 | kbps | |
m100 | Modulation depth 100%, test as defined in ISO10373 | 90% | 100% | ||
m10 | Modulation depth 10%, test as defined in ISO10373 | 7% | 30% | ||
|tPLH– tPHL| | Delta propagation delay of RXD_10 to VIN | 0 | 2.35 | µs | |
tPLH, tPHL | Propagation delay of RXD_10 to VIN | 0 | 7.07 | µs | |
tpd100 | Propagation delay of RXD_100 | 7.07 | µs | ||
tD100 | Minimum pulse duration of RxD_100 | 5 | µs |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
fPICC | Uplink subcarrier modulation frequency | 0.2 | 1 | MHz | |
VA_MOD | Modulated antenna voltage, VA_unmod = 2,3V | 0.5 | V | ||
VSUB15 | Uplink modulation subcarrier level, ISO/IEC 15693 | 10 | mV |