SLAS834C November 2012 – December 2014 RF430FRL152H , RF430FRL153H , RF430FRL154H
PRODUCTION DATA.
The RF430FRL15xH device is a 13.56-MHz transponder chip with a programmable 16-bit MSP430™ low-power microcontroller. The device features embedded universal FRAM nonvolatile memory for storage of program code or user data such as calibration and measurement data. The RF430FRL15xH supports communication, parameter setting, and configuration through the ISO/IEC 15693, ISO/IEC 18000-3 compliant RFID interface and the SPI or I2C interface. Sensor measurements are supported by the internal temperature sensor and the onboard 14-bit sigma-delta analog-to-digital converter (ADC), and digital sensors can be connected through SPI or I2C.
The RF430FRL15xH device is optimized for operation in fully passive (battery-less) or single-cell battery-powered (semi-active) mode to achieve extended battery life in portable and wireless sensing applications. FRAM is a nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and reliability of flash, all at lower total power consumption.
PART NUMBER | PACKAGE | BODY SIZE(2) |
---|---|---|
RF430FRL152H | VQFN (24) | 4 mm x 4 mm |
RF430FRL153H | VQFN (24) | 4 mm x 4 mm |
RF430FRL154H | VQFN (24) | 4 mm x 4 mm |
Changes from November 13, 2014 to December 8, 2014
Table 3-1 summarizes the available family members.
Device | FRAM (KB) |
SRAM (KB) |
Timer | 13.56-MHz ISO/IEC 15693 Front End | eUSCI_B | SD14 |
---|---|---|---|---|---|---|
RF430FRL152H | 2 | 4 | Yes | Yes | Yes | Yes |
RF430FRL153H | 2 | 4 | Yes | Yes | No | Yes |
RF430FRL154H | 2 | 4 | Yes | Yes | Yes | No |
Table 4-1 describes the signals.
TERMINAL | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ANT1 | 1 | I | Antenna input 1 |
ANT2 | 2 | I | Antenna input 2 |
VDDSW | 3 | Switched supply voltage | |
VDDB | 4 | Battery supply voltage | |
CP1 | 5 | Charge pump flying cap terminal 1 | |
CP2 | 6 | Charge pump flying cap terminal 2 | |
VDD2X | 7 | Voltage doubler output | |
P1.3 SPI_STE TA0.2 ACLK TA0CLK |
8 | I/O |
General-purpose digital I/O SPI slave transmit enable Timer_A TA0 OUT2 output ACLK output (divided by 1, 2, 4, 8, 16, or 32) Timer_A TA0 clock signal TA0CLK input |
P1.2 SPI_CLK MCLK TA0.0 |
9 | I/O |
General-purpose digital I/O SPI clock MCLK output Timer_A TA0 OUT0 output |
RST/NMI | 10 | I |
Reset input active low Non-maskable interrupt input |
P1.1 SPI_SOMI SCL ACLK TA0.2 CCI0.0 |
11 | I/O |
General-purpose digital I/O SPI slave out master in I2C clock ACLK output (divided by 1, 2, 4, or 8 ) Timer_A TA0 OUT2 output Timer_A TA0 CCR0 capture: CCI0B input, compare |
P1.0 SPI_SIMO SDA SMCLK TA0.1 CCI0.0 |
12 | I/O |
General-purpose digital I/O SPI slave in master out I2C data SMCLK output Timer0_A3 OUT1 output Timer_A TA0 CCR0 capture: CCI0A input, compare |
ADC0 | 13 | I | ADC input pin 0 |
TST2 | 14 | Internal; connect to GND | |
SVSS | 15 | Sensor reference potential | |
TST1 | 16 | Internal; connect to GND | |
ADC1 / TEMP1 | 17 | ADC input pin 1 / Resistive bias pin 1 | |
ADC2 / TEMP2 | 18 | ADC input pin 2 / Resistive bias pin 2 | |
TMS P1.7 TA0.1 TA0.0 CCI0.2 |
19 | I/O |
JTAG test mode select General-purpose digital I/O Timer_A TA0 OUT1 output Timer_A TA0 OUT0 output Timer_A TA0 CCR2 capture: CCI2B input, compare |
TDO P1.6 TA0.0 TA0.2 CCI0.2 |
20 | I/O |
JTAG test data output General-purpose digital I/O Timer_A TA0 OUT0 output Timer_A TA0 OUT2 output Timer_A TA0 CCR2 capture: CCI2A input, compare |
TDI P1.5 TA0.2 MCLK CCI0.1 |
21 | I/O |
JTAG test data input General-purpose digital I/O Timer_A TA0 OUT2 output MCLK output Timer_A TA0 CCR1 capture: CCI1B input, compare |
TCK P1.4 TA0.1 SMCLK CCI0.1 CLKIN |
22 | I/O |
JTAG test clock General-purpose digital I/O Timer_A TA0 OUT1 output SMCLK output Timer_A TA0 CCR1 capture: CCI1A input, compare External clock input pin |
VDDH | 23 | O | Rectified voltage from RF-AFE |
VDDD | 24 | Digital supply voltage | |
VSS | Pad | Ground reference, bonded to exposed pad(2) |
The GPIO port pins are multiplexed with other functions including analog peripherals and serial communication modules. The pin functions are selected by a combination of register values and device modes. For schematics of the port pins and details of the multiplexing for each, refer to Section 6.7.
The correct termination of all unused pins is listed in Table 4-2.
Pin | Potential | Comment |
---|---|---|
TDI/TMS/TCK | Open | When used for JTAG function |
RST/NMI | VCC or VSS | 10-nF capacitor to GND/VSS |
Px.0 to Px.7 | Open | Set to port function, output direction |
TDO | Open | Convention: leave TDO terminal as JTAG function |