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  • SN65DSI85-Q1 Automotive Dual-Channel MIPI DSI to Dual-Link LVDS Bridge

    • SLLSEJ4B July   2016  – June 2018 SN65DSI85-Q1

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • SN65DSI85-Q1 Automotive Dual-Channel MIPI DSI to Dual-Link LVDS Bridge
  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reset Implementation
      2. 8.3.2 Initialization Setup
      3. 8.3.3 LVDS Output Formats
      4. 8.3.4 DSI Lane Merging
      5. 8.3.5 DSI Pixel Stream Packets
      6. 8.3.6 DSI Video Transmission Specifications
      7. 8.3.7 ULPS
      8. 8.3.8 LVDS Pattern Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
    5. 8.5 Programming
      1. 8.5.1 Clock Configurations and Multipliers
    6. 8.6 Register Maps
      1. 8.6.1 Local I2C Interface Overview
        1. 8.6.1.1 Write Procedure
        2. 8.6.1.2 Read Procedure
        3. 8.6.1.3 Setting a Starting Sub-Address Procedure
      2. 8.6.2 Control and Status Registers Overview
      3. 8.6.3 CSR Bit
        1. 8.6.3.1 ID Registers (address = 0x00 to 0x08)
          1. Table 7. ID Register Field Descriptions
        2. 8.6.3.2 Reset and Clock Registers
          1. 8.6.3.2.1 Address 0x09
            1. Table 8. Address 0x09 Definitions
          2. 8.6.3.2.2 Address 0x0A
            1. Table 9. Address 0x0A Field Descriptions
          3. 8.6.3.2.3 Address 0x0B
            1. Table 10. Address 0x0B Field Descriptions
          4. 8.6.3.2.4 Address 0x0D
            1. Table 11. Address 0x0D Field Descriptions
        3. 8.6.3.3 DSI Registers
          1. 8.6.3.3.1 Address 0x10
            1. Table 12. Address 0x10 Field Descriptions
          2. 8.6.3.3.2 Address 0x11
            1. Table 13. Address 0x11 Field Descriptions
          3. 8.6.3.3.3 Address 0x12
            1. Table 14. Address 0x12 Field Descriptions
          4. 8.6.3.3.4 Address 0x13
            1. Table 15. Address 0x13 Field Descriptions
        4. 8.6.3.4 LVDS Registers
          1. 8.6.3.4.1 Address 0x18
            1. Table 16. Address 0x18 Field Descriptions
          2. 8.6.3.4.2 Address 0x19
            1. Table 17. Address 0x19 Field Descriptions
          3. 8.6.3.4.3 Address 0x1A
            1. Table 18. Address 0x1A Field Descriptions
          4. 8.6.3.4.4 Address 0x1B
            1. Table 19. Address 0x1B Field Descriptions
        5. 8.6.3.5 Video Registers
          1. 8.6.3.5.1  Address 0x20
            1. Table 20. Address 0x20 Field Descriptions
          2. 8.6.3.5.2  Address 0x21
            1. Table 21. Address 0x21 Field Descriptions
          3. 8.6.3.5.3  Address 0x22
            1. Table 22. Address 0x22 Field Descriptions
          4. 8.6.3.5.4  Address 0x23
            1. Table 23. Address 0x23 Field Descriptions
          5. 8.6.3.5.5  Address 0x24
            1. Table 24. Address 0x24 Field Descriptions
          6. 8.6.3.5.6  Address 0x25
            1. Table 25. Address 0x25 Field Descriptions
          7. 8.6.3.5.7  Address 0x26
            1. Table 26. Address 0x26 Field Descriptions
          8. 8.6.3.5.8  Address 0x27
            1. Table 27. Address 0x27 Field Descriptions
          9. 8.6.3.5.9  Address 0x28
            1. Table 28. Address 0x28 Field Descriptions
          10. 8.6.3.5.10 Address 0x29
            1. Table 29. Address 0x29 Field Descriptions
          11. 8.6.3.5.11 Address 0x2A
            1. Table 30. Address 0x2A Field Descriptions
          12. 8.6.3.5.12 Address 0x2B
            1. Table 31. Address 0x2B Field Descriptions
          13. 8.6.3.5.13 Address 0x2C
            1. Table 32. Address 0x2C Field Descriptions
          14. 8.6.3.5.14 Address 0x2D
            1. Table 33. Address 0x2D Field Descriptions
          15. 8.6.3.5.15 Address 0x2E
            1. Table 34. Address 0x2E Field Descriptions
          16. 8.6.3.5.16 Address 0x2F
            1. Table 35. Address 0x2F Field Descriptions
          17. 8.6.3.5.17 Address 0x30
            1. Table 36. Address 0x30 Field Descriptions
          18. 8.6.3.5.18 Address 0x31
            1. Table 37. Address 0x31 Field Descriptions
          19. 8.6.3.5.19 Address 0x32
            1. Table 38. Address 0x32 Field Descriptions
          20. 8.6.3.5.20 Address 0x33
            1. Table 39. Address 0x33 Field Descriptions
          21. 8.6.3.5.21 Address 0x34
            1. Table 40. Address 0x34 Field Descriptions
          22. 8.6.3.5.22 Address 0x35
            1. Table 41. Address 0x35 Field Descriptions
          23. 8.6.3.5.23 Address 0x36
            1. Table 42. Address 0x36 Field Descriptions
          24. 8.6.3.5.24 Address 0x37
            1. Table 43. Address 0x37 Field Descriptions
          25. 8.6.3.5.25 Address 0x38
            1. Table 44. Address 0x38 Field Descriptions
          26. 8.6.3.5.26 Address 0x39
            1. Table 45. Address 0x39 Field Descriptions
          27. 8.6.3.5.27 Address 0x3A
            1. Table 46. Address 0x3A Field Descriptions
          28. 8.6.3.5.28 Address 0x3B
            1. Table 47. Address 0x3B Field Descriptions
          29. 8.6.3.5.29 Address 0x3C
            1. Table 48. Address 0x3C Field Descriptions
          30. 8.6.3.5.30 Address 0x3D
            1. Table 49. Address 0x3D Field Descriptions
          31. 8.6.3.5.31 Address 0x3E
            1. Table 50. Address 0x3E Field Descriptions
        6. 8.6.3.6 IRQ Registers
          1. 8.6.3.6.1 Address 0xE0
            1. Table 51. Address 0xE0 Field Descriptions
          2. 8.6.3.6.2 Address 0xE1
            1. Table 52. Address 0xE1 Field Descriptions
          3. 8.6.3.6.3 Address 0xE2
            1. Table 53. Address 0xE2 Field Descriptions
          4. 8.6.3.6.4 Address 0xE5
            1. Table 54. Address 0xE5 Field Descriptions
          5. 8.6.3.6.5 Address 0xE6
            1. Table 55. Address 0xE6 Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Video STOP and Restart Sequence
      2. 9.1.2 Reverse LVDS Pin Order Option
      3. 9.1.3 IRQ Usage
    2. 9.2 Typical Applications
      1. 9.2.1 Typical WUXGA 18-bpp Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Script
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Typical WQXGA 24-bpp Application
        1. 9.2.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCORE Power Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Package Specific
      2. 11.1.2 Differential pairs
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • PAP|64
    • MPQF071C
Thermal pad, mechanical data (Package|Pins)
  • PAP|64
    • PPTD318A
Orderable Information
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  • sllsej4b_pm
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DATA SHEET

SN65DSI85-Q1 Automotive Dual-Channel MIPI DSI to Dual-Link LVDS Bridge

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 3A
    • Device CDM ESD Classification Level C6
  • Implements MIPI D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
  • Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
  • Supports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats
  • Suitable for 60-fps WQXGA 2560 × 1600 Resolution at 18-bpp and 24-bpp Color, and 60 fps (120 fps Equivalent) WUXGA 1920 × 1200 Resolution With 3D Graphics at 24-bpp Color
  • MIPI Front-End Configurable for Single-Channel or Dual-Channel DSI Configurations
  • Output Configurable for Single-Link or Dual-Link LVDS
  • Supports Dual-Channel DSI ODD or EVEN and LEFT or RIGHT Operating Modes
  • Supports Two Single-Channel DSI to Two Single-Link LVDS Operating Mode
  • LVDS Output-Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Mode
  • LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
  • 1.8-V Main VCC Power Supply
  • Low Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
  • LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
  • Packaged in 64-pin 10 mm × 10 mm HTQFP (PAP) PowerPAD™ IC Package

2 Applications

  • Infotainment Head Unit With Integrated Display
  • Infotainment Head Unit With Remote Display
  • Infotainment Rear-Seat Entertainment
  • Hybrid Automotive Cluster
  • Portable Navigation Device
  • Navigation
  • Industrial Human Machine Interface (HMI) and Displays

3 Description

The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHY receiver front-end
configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaces with four data lanes per link.

The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60 frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a
0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN65DSI85-Q1 HTQFP (64) 10.00 mm × 10.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application

SN65DSI85-Q1 alt_sllsej4.gif

4 Revision History

Changes from A Revision (December 2016) to B Revision

  • Deleted figure RESET and Initialization Timing Definition While VCC is HighGo
  • Changed the paragraph following Figure 8Go
  • Changed Table 1Go

Changes from * Revision (July 2016) to A Revision

  • Changed device to Production DataGo

5 Pin Configuration and Functions

PAP Package
64-Pin HTQFP With PowerPAD™
Top View
See the Layout section for layout information.

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
ADDR 64 I/O Local I2C interface target address select. See Table 6. In normal operation this pin is an input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V power rails where the SN65DSI85-Q1 VCC 1.8-V power rail is connected.
A_Y0P 46 O LVDS channel A, LVDS data output 0
A_Y0N 47 O
A_Y1P 44 O LVDS channel A, LVDS data output 1
A_Y1N 45 O
A_Y2P 41 O LVDS channel A, LVDS data output 2
A_Y2N 42 O
A_Y3P 36 O LVDS channel A, LVDS data output 3. A_Y3P and A_Y3N must be left not connected (NC) for 18-bpp panels.
A_Y3N 37 O
A_CLKP 38 O LVDS channel A, LVDS clock output
A_CLKN 39 O
B_Y0P 61 O LVDS channel B, LVDS data output 0
B_Y0N 62 O
B_Y1P 59 O LVDS channel B, LVDS data output 1
B_Y1N 60 O
B_Y2P 56 O LVDS channel B, LVDS data output 2
B_Y2N 57 O
B_Y3P 50 O LVDS channel B, LVDS data output 3. B_Y3P and B_Y3N must be left NC for 18-bpp panels.
B_Y3N 51 O
B_CLKP 53 O LVDS channel B, LVDS clock output
B_CLKN 54 O
DA0P 19 I MIPI D-PHY channel A, data lane 0; data rate up to 1 Gbps.
DA0N 20 I
DA1P 21 I MIPI D-PHY channel A, data lane 1; data rate up to 1 Gbps
DA1N 22 I
DA2P 27 I MIPI D-PHY channel A, data lane 2; data rate up to 1 Gbps.
DA2N 28 I
DA3P 29 I MIPI D-PHY channel A, data lane 3; data rate up to 1 Gbps.
DA3N 30 I
DACP 24 I MIPI D-PHY channel A, clock lane; data rate up to 1 Gbps.
DACN 25 I
DB0P 4 I MIPI D-PHY channel B, data lane 0; data rate up to 1 Gbps.
DB0N 5 I
DB1P 6 I MIPI D-PHY channel B, data lane 1; data rate up to 1 Gbps.
DB1N 7 I
DB2P 10 I MIPI D-PHY channel B, data lane 2; data rate up to 1 Gbps.
DB2N 11 I
DB3P 12 I MIPI D-PHY channel B, data lane 3; data rate up to 1 Gbps.
DB3N 13 I
DBCP 8 I MIPI D-PHY channel B, clock lane; operates up to 1 Gbps.
DBCN 9 I
EN 2 I Chip enable and reset. The device is reset (shutdown) when the EN pin is low.
GND 23 G Reference ground
26 G
52 G
IRQ 33 O Interrupt signal
REFCLK 17 I This pin is an optional external reference clock for the LVDS pixel clock. If an external reference clock is not used, this pin must be pulled to ground with an external resistor. The source of the reference clock must be placed as close as possible with a series resistor near the source to reduce EMI.
RSVD1 34 I/O Reserved. This pin must be left unconnected for normal operation.
RSVD2 1 I Reserved. This pin must be left unconnected for normal operation.
SCL 15 I Local I2C interface clock.
SDA 16 I/O Local I2C interface data
VCC 3 — 1.8-V power supply
14 —
18 —
32 —
35 —
40 —
43 —
48 —
49 —
55 —
58 —
63 —
VCORE 31 P 1.1-V output from the voltage regulator. This pin must have a 1-µF external capacitor to ground.
PowerPAD — Reference ground

 
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