The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHY receiver front-end
configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaces with four data lanes per link.
The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60 frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a
0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN65DSI85-Q1 | HTQFP (64) | 10.00 mm × 10.00 mm |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ADDR | 64 | I/O | Local I2C interface target address select. See Table 6. In normal operation this pin is an input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V power rails where the SN65DSI85-Q1 VCC 1.8-V power rail is connected. |
A_Y0P | 46 | O | LVDS channel A, LVDS data output 0 |
A_Y0N | 47 | O | |
A_Y1P | 44 | O | LVDS channel A, LVDS data output 1 |
A_Y1N | 45 | O | |
A_Y2P | 41 | O | LVDS channel A, LVDS data output 2 |
A_Y2N | 42 | O | |
A_Y3P | 36 | O | LVDS channel A, LVDS data output 3. A_Y3P and A_Y3N must be left not connected (NC) for 18-bpp panels. |
A_Y3N | 37 | O | |
A_CLKP | 38 | O | LVDS channel A, LVDS clock output |
A_CLKN | 39 | O | |
B_Y0P | 61 | O | LVDS channel B, LVDS data output 0 |
B_Y0N | 62 | O | |
B_Y1P | 59 | O | LVDS channel B, LVDS data output 1 |
B_Y1N | 60 | O | |
B_Y2P | 56 | O | LVDS channel B, LVDS data output 2 |
B_Y2N | 57 | O | |
B_Y3P | 50 | O | LVDS channel B, LVDS data output 3. B_Y3P and B_Y3N must be left NC for 18-bpp panels. |
B_Y3N | 51 | O | |
B_CLKP | 53 | O | LVDS channel B, LVDS clock output |
B_CLKN | 54 | O | |
DA0P | 19 | I | MIPI D-PHY channel A, data lane 0; data rate up to 1 Gbps. |
DA0N | 20 | I | |
DA1P | 21 | I | MIPI D-PHY channel A, data lane 1; data rate up to 1 Gbps |
DA1N | 22 | I | |
DA2P | 27 | I | MIPI D-PHY channel A, data lane 2; data rate up to 1 Gbps. |
DA2N | 28 | I | |
DA3P | 29 | I | MIPI D-PHY channel A, data lane 3; data rate up to 1 Gbps. |
DA3N | 30 | I | |
DACP | 24 | I | MIPI D-PHY channel A, clock lane; data rate up to 1 Gbps. |
DACN | 25 | I | |
DB0P | 4 | I | MIPI D-PHY channel B, data lane 0; data rate up to 1 Gbps. |
DB0N | 5 | I | |
DB1P | 6 | I | MIPI D-PHY channel B, data lane 1; data rate up to 1 Gbps. |
DB1N | 7 | I | |
DB2P | 10 | I | MIPI D-PHY channel B, data lane 2; data rate up to 1 Gbps. |
DB2N | 11 | I | |
DB3P | 12 | I | MIPI D-PHY channel B, data lane 3; data rate up to 1 Gbps. |
DB3N | 13 | I | |
DBCP | 8 | I | MIPI D-PHY channel B, clock lane; operates up to 1 Gbps. |
DBCN | 9 | I | |
EN | 2 | I | Chip enable and reset. The device is reset (shutdown) when the EN pin is low. |
GND | 23 | G | Reference ground |
26 | G | ||
52 | G | ||
IRQ | 33 | O | Interrupt signal |
REFCLK | 17 | I | This pin is an optional external reference clock for the LVDS pixel clock. If an external reference clock is not used, this pin must be pulled to ground with an external resistor. The source of the reference clock must be placed as close as possible with a series resistor near the source to reduce EMI. |
RSVD1 | 34 | I/O | Reserved. This pin must be left unconnected for normal operation. |
RSVD2 | 1 | I | Reserved. This pin must be left unconnected for normal operation. |
SCL | 15 | I | Local I2C interface clock. |
SDA | 16 | I/O | Local I2C interface data |
VCC | 3 | — | 1.8-V power supply |
14 | — | ||
18 | — | ||
32 | — | ||
35 | — | ||
40 | — | ||
43 | — | ||
48 | — | ||
49 | — | ||
55 | — | ||
58 | — | ||
63 | — | ||
VCORE | 31 | P | 1.1-V output from the voltage regulator. This pin must have a 1-µF external capacitor to ground. |
PowerPAD | — | Reference ground |