SLLS926B December   2008  – November 2014 SN65EPT22

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Simplified Schematic
  5. 5Revision History
  6. 6Pin Configuration and Functions
  7. 7Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Power Dissipation Ratings
    4. 7.4 Thermal Information
    5. 7.5 Key Attributes
    6. 7.6 TTL Input DC Characteristics
    7. 7.7 PECL Output DC Characteristics
    8. 7.8 AC Characteristics
    9. 7.9 Typical Characteristics
  8. 8Device and Documentation Support
    1. 8.1 Trademarks
    2. 8.2 Electrostatic Discharge Caution
    3. 8.3 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Dual 3.3V LVTTL to LVPECL Buffer
  • Operating Range
    • LVPECL VCC = 3.0 V to 3.6 V With
      GND = 0 V
  • Support for Clock Frequencies to 2.0 GHz (typ)
  • 420 ps Typical Propagation Delay
  • Deterministic HIGH Output Value for Open Input Conditions
  • Built-in Temperature Compensation
  • Drop in Compatible to MC100ELT23
  • PNP Single Ended Inputs for Minimal Loading

2 Applications

  • Data and Clock Transmission Over Backplane
  • Signaling Level Conversion

3 Description

The SN65EPT22 is a low power dual LVTTL to LVPECL translator device. The device includes circuitry to maintain known logic HIGH level when inputs are in open condition. The SN65EPT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN65EPT22 SOIC (8) 4.90mm x 3.91mm
VSSOP (8) 3.00mm x 3.00mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

fp_schematic_slls926.gif