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  • SN65LVCP114 14.2-Gbps Quad 1:2-2:1 Mux, Linear-Redriver With Signal Conditioning

    • SLLSEA8A January   2012  – March 2016 SN65LVCP114

      PRODUCTION DATA.  

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  • SN65LVCP114 14.2-Gbps Quad 1:2-2:1 Mux, Linear-Redriver With Signal Conditioning
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics (VCC 2.5 V ±5%)
    6. 7.6 Electrical Characteristics (VCC 3.3 V ±5%)
    7. 7.7 Electrical Characteristics (VCC 3.3 V ±5%, 2.5 V ±5%)
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Circuits
    2. 8.2 Equivalent Input and Output Schematic Diagrams
    3. 8.3 Functional Definitions
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power Down
      2. 9.3.2  Lane Enable
      3. 9.3.3  Gain and Equalization
      4. 9.3.4  VOD
      5. 9.3.5  AGC
      6. 9.3.6  GPIO or I2C Configuration
      7. 9.3.7  Fast Switching
      8. 9.3.8  Power-Down Input Stages
      9. 9.3.9  Disable Output Lanes
      10. 9.3.10 Polarity Switch
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Loopback
      3. 9.4.3 Diagnostic
    5. 9.5 Programming
      1. 9.5.1 Two-Wire Serial Interface and Control Logic
    6. 9.6 Register Maps
      1. 9.6.1 SN65LVCP114 Register Mapping Information
        1. 9.6.1.1  Register 0x00
        2. 9.6.1.2  Register 0x01
        3. 9.6.1.3  Register 0x02
        4. 9.6.1.4  Register 0x03
        5. 9.6.1.5  Register 0x04
        6. 9.6.1.6  Register 0x06
        7. 9.6.1.7  Register 0x07
        8. 9.6.1.8  Register 0x08
        9. 9.6.1.9  Register 0x0A
        10. 9.6.1.10 Register 0x0B
        11. 9.6.1.11 Register 0x0C
        12. 9.6.1.12 Register 0x0D
        13. 9.6.1.13 Register 0x0F
        14. 9.6.1.14 Register 0x10
        15. 9.6.1.15 Register 0x11
        16. 9.6.1.16 Register 0x12
        17. 9.6.1.17 Register Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Transmit-Side Typical Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Receive-Side Typical Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documenation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
  15. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • ZJA|167
    • MPBGA19
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sllsea8a_oa
  • sllsea8a_pm
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DATA SHEET

SN65LVCP114 14.2-Gbps Quad 1:2-2:1 Mux, Linear-Redriver With Signal Conditioning

1 Features

  • Quad 2:1 Mux and 1:2 Demux
  • Multi-Rate Operation up to 14.2 Gbps Serial Data Rate
  • Linear Receiver Equalization Which Increases Margin at System Level of Decision Feedback Equalizer
  • Bandwidth: 18 GHz, Typical
  • Per-Lane P/N Pair Inversion
  • Port or Single Lane Switching
  • Low Power: 150 mW/Channel, Typical
  • Loopback Mode on All Three Ports
  • I2C Control in Addition to GPIO
  • DIAG Mode That Outputs Data of Line Side Port to Both Fabric Side Ports
  • 2.5-V or 3.3-V Single Power Supply
  • PBGA Package 12-mm × 12-mm × 1-mm, 0.8-mm Terminal Pitch
  • Excellent Impedance Matching to 100-Ω PCB Transmission Lines
  • Small Package Size Provides Board Real Estate Saving
  • Adjustable Output Swing Provides Flexible EMI and Crosstalk Control
  • Low Power
  • Supports 10GBASE-KR Applications With Ability to Transparency for Link Training

2 Applications

  • High-Speed Redundancy Switch in Telecom and Data Communication
  • Backplane Interconnect for 10G-KR, 16GFC

3 Description

The SN65LVCP114 device is an asynchronous, protocol-agnostic, low-latency QUAD mux, linear-redriver optimized for use in systems operating at up to 14.2 Gbps. The device linearly compensates for channel loss in backplane and active-cable applications. The architecture of SN65LVCP114 linear-redriver is designed to work effectively with ASIC or FPGA products implementing digital equalization using decision feedback equalizer (DFE) technology. The SN65LVCP114 mux, linear-redriver preserves the integrity (composition) of the received signal, ensuring optimum DFE and system performance. The SN65LVCP114 provides a low-power mux-demux, linear-redriver solution while at the same time extending the effectiveness of DFE.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN65LVCP114 NFBGA (167) 12.00 mm × 12.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

SN65LVCP114 Typical Implementation

SN65LVCP114 typ_imple_llsea8.png

4 Revision History

Changes from * Revision (January 2012) to A Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
  • Removed Typical Eq Gain Profile Curve graph in Typical Characteristics Go

5 Description (continued)

SN65LVCP114 is configurable through GPIO or an I2C interface.

A single 2.5-V or 3.3-V power supply supports the operation of the SN65LVCP114.

The SN65LVCP114 is packaged in a 12-mm × 12-mm × 1-mm PBGA package with 0.8-mm pitch.

The SN65LVCP114 has three ports; each port is a quad lane. The switch logic of SN65LVCP114 can be implemented to support a 2:1 MUX per lane, 1:2 DEMUX per lane, and independent lane switching. The receive equalization can be independently programmed for each of the ports. The SN65LVCP114 supports loopback on all three ports.

Table 1. Recommended Maximum Board Temperature

LOOP_A LOOP_B LOOP_C DIAG MAXIMUM BOARD TEMPERATURE(1)
VCC = 2.5 V VCC = 3.3 V
VOD = LOW VOD = HIGH VOD = LOW VOD = HIGH
LOW LOW LOW LOW 85°C 85°C 85°C 75°C
LOW LOW LOW HIGH 85°C 85°C 75°C System Specific (2)
LOW LOW HIGH LOW 85°C 85°C 85°C 75°C
LOW LOW HIGH HIGH 85°C 85°C 85°C 75°C
LOW HIGH LOW LOW 85°C 85°C 75°C System Specific(2)
LOW HIGH LOW HIGH 85°C 85°C 75°C System Specific(2)
LOW HIGH HIGH LOW 85°C 85°C 75°C System Specific(2)
LOW HIGH HIGH HIGH 85°C 85°C 75°C System Specific(2)
HIGH LOW LOW LOW 85°C 85°C 85°C 75°C
HIGH LOW LOW HIGH 85°C 85°C 75°C System Specific(2)
HIGH LOW HIGH LOW 85°C 85°C 85°C 75°C
HIGH LOW HIGH HIGH 85°C 85°C 75°C System Specific(2)
HIGH HIGH LOW LOW 85°C 85°C 75°C System Specific(2)
HIGH HIGH LOW HIGH 85°C 85°C 75°C System Specific(2)
HIGH HIGH HIGH LOW 85°C 85°C 75°C System Specific(2)
HIGH HIGH HIGH HIGH 85°C 85°C 75°C System Specific(2)
(1) Maximum board temperature is allowed as long as the device maximum junction temperature is not exceeded.
(2) Texas Instruments recommends a system thermal and device use case power analysis to decide possible use of a heat sink.

 
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