Refer to the PDF data sheet for device specific package drawings
These TTL hex buffers and drivers feature high-voltage open-collector outputs for interfacing with high-level circuits (such as MOS) or for driving high-current loads (such as lamps or relays), and also are characterized for use as buffers for driving TTL inputs. The SN5407 and SN7407 devices have minimum breakdown voltages of 30 V, and the SN5417 and SN7417 devices have minimum breakdown voltages of 15 V. The maximum sink current is 30 mA for the SN5407 and SN5417 devices and 40 mA for the SN7407 and SN7417 devices.
These devices perform the Boolean function Y = A in positive logic.
These circuits are completely compatible with most TTL families. Inputs are diode clamped to minimize transmission-line effects, which simplifies design. Typical power dissipation is 145 mW, and average propagation delay time is 14 ns.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SNx407J, SNx417J |
CDIP (14) | 19.56 mm × 6.92 mm |
SN74x7D | SOIC (14) | 8.65 mm × 3.91 mm |
SN74x7N | PDIP (14) | 19.30 mm × 6.35 mm |
SNJ5407FK | LCCC (20) | 8.89 mm × 8.89 mm |
SNJ5407W | CFP (14) | 9.21 mm × 5.97 mm |
Changes from G Revision (May 2004) to H Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOIC, PDIP, CDIP, CFP | LCCC | ||
1A | 1 | 2 | I | Input 1 |
1Y | 2 | 3 | O | Output 1 |
2A | 3 | 4 | I | Input 2 |
2Y | 4 | 6 | O | Output 2 |
3A | 5 | 8 | I | Input 3 |
3Y | 6 | 9 | O | Output 3 |
4A | 9 | 13 | I | Input 4 |
4Y | 8 | 12 | O | Output 4 |
5A | 11 | 16 | I | Input 5 |
5Y | 10 | 14 | O | Output 5 |
6A | 13 | 19 | I | Input 6 |
6Y | 12 | 18 | O | Output 6 |
GND | 7 | 10 | — | Ground Pin |
NC | — | 1, 5, 7, 11, 15, 17 | — | No Connect |
VCC | 14 | 20 | — | Power Pin |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | 7 | V | ||
VI | Input voltage(2) | 5.5 | V | ||
VO | Output voltage(2)(3) | SN5407, SN7407 | 30 | V | |
SN5417, SN7417 | 15 | ||||
TJ | Junction temperature | 150 | ºC | ||
Tstg | Storage temperature | –65 | 150 | ºC |
VALUE | UNIT | |||
---|---|---|---|---|
SN7407 AND SN7417 | ||||
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
SN5407 AND SN5417 | ||||
V(ESD) | Electrostatic discharge | Human-body model (HBM) | ±2000 | V |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage | SN5407, SN5417 | 4.5 | 5 | 5.5 | V |
SN7407, SN7417 | 4.75 | 5 | 5.25 | |||
VIH | High-level input voltage | 2 | V | |||
VIL | Low-level input voltage | 0.8 | V | |||
VOH | High-level output voltage | SN5407, SN7407 | 30 | V | ||
SN5417, SN7417 | 15 | |||||
IOL | Low-level output current | SN5407, SN5417 | 30 | mA | ||
SN7407, SN7417 | 40 | |||||
TA | Operating free-air temperature | SN5407, SN5417 | –55 | 125 | °C | |
SN7407, SN7417 | 0 | 70 |
THERMAL METRIC(1) | SN7407 | SN7417 | UNIT | ||||
---|---|---|---|---|---|---|---|
D (SOIC) | N (PDIP) | NS (SO) | D (SOIC) | N (PDIP) | |||
14 PINS | 14 PINS | 14 PINS | 14 PINS | 14 PINS | |||
RθJA | Junction-to-ambient thermal resistance(2) | 86.8 | 52.1 | 85.9 | 88.8 | 52.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 47.1 | 39.4 | 43.9 | 50.4 | 39.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 41 | 32 | 44.7 | 43 | 32 | °C/W |
ψJT | Junction-to-top characterization parameter | 15.6 | 24.2 | 14.6 | 16.5 | 24.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 40.8 | 31.8 | 44.4 | 42.8 | 31.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIK | Input clamp voltage | VCC = MIN, II = –12 mA | –1.5 | V | |||
VOL | Low-level output voltage | VCC = MIN, VIL = 0.8 V |
IOL = 16 mA | 0.4 | V | ||
IOL = 30 mA, SN5407, SN5417 | 0.7 | ||||||
IOL = 40 mA, SN7407, SN7417 | 0.7 | ||||||
IOH | High-level output current | VCC = MIN, VIH = 2 V |
VOH = 30 V, SN5407, SN7407 | 0.25 | mA | ||
VOH = 15 V, SN5417, SN7417 | 0.25 | ||||||
II | Input current | VCC = MAX, VI = 5.5 V | 1 | mA | |||
IIH | High-level input current | VCC = MAX, VIH = 2.4 V | 40 | µA | |||
IIL | Low-level input current | VCC = MAX, VIL = 0.4 V | –1.6 | mA | |||
ICCH | High-level supply current | VCC = MAX | 29 | 41 | mA | ||
ICCL | Low-level supply current | VCC = MAX | 21 | 30 | mA |
PARAMETER | FROM (INPUT) | TO (OUTPUT) | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|---|
tPLH | A | Y | RL = 110 Ω, CL = 15 pF | 6 | 10 | ns | |
tPHL | 20 | 30 | |||||
tPLH | A | Y | RL = 150 Ω, CL = 50 pF | 15 | ns | ||
tPHL | 26 |
The SN74x7 is a high sink current capable open-collector buffer. This device is high-voltage tolerant on the output of up to 30 V on the SNx407 model and 15 V on the SNx417 model. The SN74x7 is also useful for converting TTL voltage levels to MOS levels.
The SNx407 and SNx417 devices are ideal for high voltage outputs. The SNx407 device has a maximum output voltage 30 V and the SNx417 device has a maximum output voltage 15 V.
The high sink current is up to 40 mA for the SN74x7.
Table 1 lists the functions of the devices.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The SN74x7 device is a high-drive, open-collector device that is used for multiple buffer-type functions. The device produces 30 mA of drive current. Therefore, this device is ideal for driving multiple inputs and for high-speed applications up to 100 MHz. The outputs are high voltage tolerant up to 30 V for the SNx407.
Avoid bus contention because it can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads; therefore, routing and load conditions must be considered to prevent ringing.
The power supply can be any voltage between the minimum and maximum supply voltage rating (see Recommended Operating Conditions).
Each VCC pin must have a good bypass capacitor to prevent power disturbance. TI recommends 0.1 µF for devices with a single supply. If there are multiple VCC pins, then TI recommends 0.01 µF or 0.022 µF for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. A 0.1 µF and a 1 µF are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best results.
When using multiple bit logic devices inputs must never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they are tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver.
For related documentation see the following:
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS | PRODUCT FOLDER | SAMPLE & BUY | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
SN5407 | Click here | Click here | Click here | Click here | Click here |
SN5417 | Click here | Click here | Click here | Click here | Click here |
SN7407 | Click here | Click here | Click here | Click here | Click here |
SN7417 | Click here | Click here | Click here | Click here | Click here |
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
SLYZ022 — TI Glossary.
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