Data Sheet
SN74AHCT138Q-Q1 Automotive 3-Line to 8-Line Decoders/Demultiplexers
1 Features
- Qualified for Automotive Applications
- EPIC (Enhanced-Performance Implanted CMOS) Process
- Inputs Are TTL-Voltage Compatible
- Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
- Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception
- Latch-Up Performance Exceeds 250mA Per JESD 17
- ESD Protection Exceeds 2000V Per MIL-STD-833, Method 3015
2 Description
The SN74AHCT138Q 3-line to 8-line decoder/demultiplexer is designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
Package Information
| PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) | BODY SIZE(3) |
|---|---|---|---|
| SN74AHCT138Q-Q1 | BQB (WQFN, 16) | 3.5mm x 2.5mm | 3.5mm x 2.5mm |
| D (SOIC, 16) | 9.9mm x 6mm | 9.9mm x 3.9mm | |
| PW (TSSOP, 16) | 5.00mm x 6.4mm | 5.00mm x 4.40mm |
(1) For more information, see Section 10.
(2) The package size (length × width)
is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is
a nominal value and does not include pins.
Logic Diagram (Positive Logic)