SCES593F JULY 2004 – July 2017 SN74AUP1G80
PRODUCTION DATA.
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see AUP – The Lowest-Power Family). This product also maintains excellent signal integrity (see Excellent Signal Integrity).
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN74AUP1G80DBV | SOT-23 (5) | 1.60 mm × 2.90 mm |
SN74AUP1G80DCK | SC70 (5) | 1.25 mm × 2.00 mm |
SN74AUP1G80DRY | SON (6) | 1.00 mm × 1.45 mm |
SN74AUP1G80DSF | SON (6) | 1.00 mm × 1.00 mm |
SN74AUP1G80YFP | DSBGA (6) | 0.76 mm × 1.16 mm |
SN74AUP1G80YZP | DSBGA (5) | 0.89 mm × 1.39 mm |
SN74AUP1G80DPW | X2SON (5) | 0.80 mm × 0.80 mm |