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SN74AXCH1T45 Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Inputs
SCES883C
December 2018 – September 2020
SN74AXCH1T45
PRODUCTION DATA
CONTENTS
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SN74AXCH1T45 Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Inputs
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics, VCCA = 0.7 V
6.7
Switching Characteristics, VCCA = 0.8 V
6.8
Switching Characteristics, VCCA = 0.9 V
6.9
Switching Characteristics, VCCA = 1.2 V
6.10
Switching Characteristics, VCCA = 1.5 V
6.11
Switching Characteristics, VCCA = 1.8 V
6.12
Switching Characteristics, VCCA = 2.5 V
6.13
Switching Characteristics, VCCA = 3.3 V
6.14
Operating Characteristics: TA = 25°C
6.15
Typical Characteristics
7
Parameter Measurement Information
7.1
Load Circuit and Voltage Waveforms
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Standard CMOS Inputs
8.3.2
Balanced High-Drive CMOS Push-Pull Outputs
8.3.3
Partial Power Down (Ioff)
8.3.4
VCC Isolation
8.3.5
Over-Voltage Tolerant Inputs
8.3.6
Negative Clamping Diodes
8.3.7
Fully Configurable Dual-Rail Design
8.3.8
Supports High-Speed Translation
8.3.9
Bus-Hold Data Inputs
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
Enable Times
9.2
Typical Applications
9.2.1
Interrupt Request Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curve
9.2.2
Universal Asynchronous Receiver-Transmitter (UART) Interface Application
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
DRY|6
MPDS221F
DCK|6
MPDS114F
DTQ|6
MUSS003A
DBV|6
MPDS026Q
Thermal pad, mechanical data (Package|Pins)
DRY|6
QFND138E
Orderable Information
sces883c_oa
sces883c_pm
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DATA SHEET
SN74AXCH1T45 Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Inputs
1
Features
Fully Configurable Dual-Rail Design Allows Each Port to Operate With a Power Supply Range from 0.65 V to 3.6 V
Operating Temperature: –40°C to +125°C
Glitch-Free Power Supply Sequencing
Bus-hold on Data Inputs Eliminates the Need for External Pullup or Pulldown Resistors
Maximum Quiescent Current (I
CCA
+ I
CCB
) of 10 µA (85°C Maximum) and 16 µA (125°C Maximum)
Up to 500-Mbps Support When Translating from 1.8 to 3.3 V
V
CC
Isolation Feature
If Either V
CC
Input is Below 100 mV, All I/Os Outputs are Disabled and Become High-Impedance
I
off
Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
8000-V Human Body Model
1000-V Charged-Device Model
2
Applications
Personal Electronics
Enterprise and Communications
Wireless Infrastructure
Building Automation
Electronic Point of Sale
Enterprise Solid State Drive