SCDS019M May   1995  – December 2015 SN74CBT3251

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristic
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|16
  • PW|16
  • DBQ|16
  • RGY|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 5-Ω Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Low Crosstalk Between Switches
  • Fast Switching and Propagation Speeds
  • Operating Temperature Range:
    –40°C to 85°C

2 Applications

  • Digital Radio
  • Signal Gating
  • Factory Automation
  • Televisions
  • Appliances
  • Programmable Logic Circuits
  • Sensors

3 Description

The SN74CBT3251 is a 1-of-8 high-speed TTL-compatible FET multiplexer and demultiplexer. The low ON-state resistance of the switch allows connections to be made with minimal propagation delay.

When output enable (OE) is low, the SN74CBT3251 is enabled, and S0, S1, and S2 select one of the B outputs for the A-input data.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74CBT3251RGY VQFN (16) 3.50 mm × 4.00 mm
SN74CBT3251DBQ SSOP (16) 3.90 mm × 4.90 mm
SN74CBT3251PW TSSOP (16) 4.40 mm × 5.00 mm
SN74CBT3251DB SSOP (16) 5.30 mm × 6.20 mm
SN74CBT3251D SOIC (16) 3.91 mm × 9.90 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Diagram of the SN74CBT3251

SN74CBT3251 logic_diag.gif