Refer to the PDF data sheet for device specific package drawings
This device contains two independent 4-input NAND gates. Each gate performs the Boolean function Y = A ● B ● C ● D in positive logic.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN74HC20D | SOIC (14) | 8.70 mm × 3.90 mm |
SN74HC20N | PDIP (14) | 19.30 mm × 6.40 mm |
SN74HC20NS | SO (14) | 10.20 mm × 5.30 mm |
SN74HC20PW | TSSOP (14) | 5.00 mm × 4.40 mm |
SN54HC20J | CDIP (14) | 21.30 mm × 7.60 mm |
SN54HC20W | CFP (14) | 9.20 mm × 6.29 mm |
SN54HC20FK | LCCC (20) | 8.90 mm × 8.90 mm |
Changes from Revision F (August 2003) to Revision G (April 2021)
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | D, N, NS, PW, J, or W | FK | ||
1A | 1 | 2 | Input | Channel 1, Input A |
1B | 2 | 3 | Input | Channel 1, Input B |
NC | 3, 11 | 1, 4, 5, 7, 11, 15, 16, 17 | — | Not internally connected |
1C | 4 | 6 | Input | Channel 1, Input C |
1D | 5 | 8 | Input | Channel 1, Input D |
1Y | 6 | 9 | Output | Channel 1, Output Y |
GND | 7 | 10 | — | Ground |
2Y | 8 | 12 | Output | Channel 2, Output Y |
2A | 9 | 13 | Input | Channel 2, Input A |
2B | 10 | 14 | Input | Channel 2, Input B |
2C | 12 | 18 | Input | Channel 2, Input C |
2D | 13 | 19 | Input | Channel 2, Input D |
VCC | 14 | 20 | — | Positive Supply |