Refer to the PDF data sheet for device specific package drawings
These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC241 devices are organized as two 4-bit buffers/drivers with separate output-enable (1OE and 2OE) inputs. When 1OE is low or 2OE is high, the device passes noninverted data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs for the respective buffers/drivers are in the high-impedance state.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
SN74HC241DW | SOIC (20) | 12.80 mm × 7.50 mm |
SN74HC241N | PDIP (20) | 25.40 mm × 6.35 mm |
SN74HC241NSR | SO (20) | 15.00 mm × 5.30 mm |
SN74HC241PW | TSSOP (20) | 6.50 mm × 4.40 mm |
SN54HC241J | CDIP (20) | 26.92 mm × 6.92 mm |
SNJ54HC241FK | LCCC (20) | 8.89 mm × 8.45 mm |
Changes from Revision D (January 2022) to Revision E (May 2022)
Changes from Revision C (August 2003) to Revision D (January 2022)