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  • SN74LV595A-Q1 8-Bit Shift Registers With 3-State Output Registers

    • SCLS539G August   2003  – March 2023 SN74LV595A-Q1

      PRODMIX  

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  • SN74LV595A-Q1 8-Bit Shift Registers With 3-State Output Registers
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements, VCC = 2.5 V ± 0.2 V
    7. 6.7  Timing Requirements, VCC = 3.3 V ± 0.3 V
    8. 6.8  Timing Requirements, VCC = 5 V ± 0.5 V
    9. 6.9  Switching Characteristics, VCC = 2.5 V ± 0.2 V
    10. 6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    11. 6.11 Switching Characteristics, VCC = 5 V ± 0.5 V
    12. 6.12 Timing Diagrams
    13. 6.13 Noise Characteristics
    14. 6.14 Operating Characteristics
    15. 6.15 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS 3-State Outputs
      2. 8.3.2 Latching Logic
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 Wettable Flanks
      5. 8.3.5 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Power Considerations
      2. 9.2.2 Input Considerations
      3. 9.2.3 Output Considerations
      4. 9.2.4 Detailed Design Procedure
      5. 9.2.5 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
  12. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • PW|16
    • MPDS361A
  • BQB|16
    • MPQF539A
Thermal pad, mechanical data (Package|Pins)
  • BQB|16
    • PPTD365
Orderable Information
  • scls539g_oa
  • scls539g_pm
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DATA SHEET

SN74LV595A-Q1 8-Bit Shift Registers With 3-State Output Registers

1 Features

  • Qualified for automotive applications
  • Available in wettable flank QFN (WBQB) package
  • Customer-specific configuration control can be supported along with major-change approval
  • 2-V to 5.5-V VCC operation
  • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Supports mixed-mode voltage operation on all ports
  • 8-bit serial-in, parallel-out shift
  • Ioff supports partial-power-down mode operation
  • Shift register has direct clear

2 Applications

  • Output expansion
  • LED matrix control
  • 7-segment display control

3 Description

The SN74LV595A-Q1 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH' are in the high-impedance state.

The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Package Information(1)
PART NUMBERPACKAGE BODY SIZE (NOM)
SN74LV595A-Q1PW (TSSOP, 16)5.00 mm × 4.40 mm
WBQB (WQFN, 16)3.60 mm × 2.60 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20211015-SS0I-66P0-J2PR-6DVV9SDRTXZD-low.gif Logic Diagram (Positive Logic)

4 Revision History

Changes from Revision F (November 2022) to Revision G (March 2023)

  • Updated structural layout of document to current standardsGo
  • Updated thermal values for PW package from RθJA = 108 to 138.7, RθJC(top) = 40.8 to 69.1, RθJB = 51.1 to 81.8, ΨJT = 3.8 to 20.3, ΨJB = 50.6 to 81.3, all values in °C/W Go

Changes from Revision E (June 2022) to Revision F (November 2022)

  • Changed the status of the data sheet from: Advanced Information to: Production Data Go

5 Pin Configuration and Functions

GUID-77437250-2CCB-4CED-9FFE-AFDA41812B6A-low.gifFigure 5-1 PW Package,
16-Pin TSSOP
(Top View)
GUID-20200810-CA0I-Q9NM-WJZN-2VVL5S1MZF0C-low.gifFigure 5-2 WBQB Package,
16-Pin WQFN
Transparent (Top View)
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
GND8GGround
OE13IOutput Enable Pin
QA15OQA Output
QB1OQB Output
QC2OQC Output
QD3OQD Output
QE4OQE Output
QF5OQF Output
QG6OQG Output
QH7OQH Output
QH'9OQH' Output
SRCLR10ISRCLR Input
SRCLK11ISRCLK Input
RCLK12IRCLK Input
SER14ISER Input
VCC16PPositive Supply

PAD

——

Thermal Pad(2)

(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
(2) WBQB Package Only

 
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