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  • SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

    • SCES560G March   2004  – June 2015 SN74LVC1G175

      PRODUCTION DATA.  

  • CONTENTS
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  • SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements, -40°C to 85°C
    7. 6.7  Timing Requirements, -40°C to 125°C
    8. 6.8  Switching Characteristics, -40°C to 85°C
    9. 6.9  Switching Characteristics, -40°C to 85°C
    10. 6.10 Switching Characteristics, -40°C to 125°C
    11. 6.11 Operating Characteristics
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DRY|6
    • MPDS221F
  • YZP|6
    • MXBG347
  • DCK|6
    • MPDS114F
  • DBV|6
    • MPDS026Q
Thermal pad, mechanical data (Package|Pins)
  • DRY|6
    • QFND617
Orderable Information
  • sces560g_oa
  • sces560g_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
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DATA SHEET

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features

  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Max tpd of 4.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

2 Applications

  • TV/Set Top Box/Audio
  • EPOS (Electronic Point-of-Sale)
  • Motor Drives
  • PC/Notebook
  • Servers
  • Factory Automation and Control
  • Tablets
  • Medical Healthcare and Fitness
  • Smart Grid
  • Telecom Infrastructure
  • Enterprise Switching
  • Projectors
  • Storage

3 Description

This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G175 device has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data on D.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1G175DBV SOT-23 (6) 2.90 mm × 1.60 mm
SN74LVC1G175DCK SC70 (6) 2.00 mm × 1.25 mm
SN74LVC1G175DRY SON (6) 1.45 mm × 1.00 mm
SN74LVC1G175YZP DSBGA (6) 1.41 mm × 0.91 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN74LVC1G175 ld_ces560.gif

4 Revision History

Changes from F Revision (December 2013) to G Revision

  • Added ApplicationsGo
  • Added Device Information tableGo
  • Added ESD Ratingss table.Go
  • Added Thermal Information tableGo
  • Added Typical Characteristics.Go

Changes from E Revision (June 2008) to F Revision

  • Updated document to new TI data sheet format.Go
  • Deleted Ordering Information table.Go
  • Updated Features.Go

5 Pin Configuration and Functions

DBV Package
6-Pin SOT-23
Top View
SN74LVC1G175 po_ces560_DBV.gif
DCK Package
6-Pin SC70
Top View
SN74LVC1G175 po_ces560_DCK.gif
DRY Package
6-Pin SON
Top View
SN74LVC1G175 po2_ces560_DRY.gif
YZP Package
6-Pin DSBGA
Bottom View
SN74LVC1G175 po2_ces560_YZP.gif
See mechanical drawings for dimensions.

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CLK 1 I Clock Input
CLR 6 I Clear Data Input
D 3 I Data Input
GND 2 — Ground
Q 4 O Output
VCC 5 — Power

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
VI Input voltage –0.5 6.5 V
VO Voltage applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VO Voltageapplied to any output in the high or low state(2)(3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage Operating 1.65 5.5 V
Data retention only 1.5
VIH High-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC V
VCC = 2.3 V to 2.7 V 1.7
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VIL Low-level input voltage VCC = 1.65 V to 1.95 V 0.35 × VCC V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
IOH High-level output current VCC = 1.65 V –4 mA
VCC = 2.3 V –8
VCC = 3 V –16
–24
VCC = 4.5 V –32
IOL Low-level output current VCC = 1.65 V 4 mA
VCC = 2.3 V 8
VCC = 3 V 16
24
VCC = 4.5 V 32
Δt/Δv Input transition rise or fall rate VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 ns/V
VCC = 3.3 V ± 0.3 V 10
VCC = 5 V ± 0.5 V 10
TA Operating free-air temperature –40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004.

6.4 Thermal Information

THERMAL METRIC(1) SN74LVC1G175 UNIT
DBV (SOT-23) DCK (SC70) DRY (SON) YZP (DSBGA)
6 PINS 6 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 165 259 234 123 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC –40°C to 85°C –40°C to 125°C UNIT
MIN TYP(1) MAX MIN TYP(1) MAX
VOH IOH = –100 µA 1.65 V to 5.5 V VCC  – 0.1 VCC  – 0.1 V
IOH = –4 mA 1.65 V 1.2 1.2
IOH = –8 mA 2.3 V 1.9 1.9
IOH = –16 mA 3 V 2.4 2.4
IOH = –24 mA 2.3 2.3
IOH = –32 mA 4.5 V 3.8 3.8
VOL IOL = 100 µA 1.65 V to 5.5 V 0.1 0.1 V
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.3 0.3
IOL = 16 mA 3 V 0.4 0.4
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.55
II VI = 5.5 V or GND 0 to 5.5 V ±1 ±1 µA
Ioff VI or VO = 5.5 V 0 ±10 ±10 µA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 10 µA
ΔICC One input at VCC  – 0.6 V,
Other inputs at VCC or GND		 3 V to 5.5 V 500 500 µA
Ci VI = VCC or GND 3.3 V 3 3 pF
(1) All typical values are at VCC = 3.3 V, TA = 25°C.

6.6 Timing Requirements, –40°C to 85°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
–40°C to 85°C UNIT
VCC = 1.8 V
± 0.15 V		 VCC = 2.5 V
± 0.2 V		 VCC = 3.3 V
± 0.3 V		 VCC = 5 V
± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 100 125 150 175 MHz
tw Pulse duration CLR Low 5.6 3 2.8 2.5 ns
CLK High or low 3.5 3 2.8 2.5
tsu Setup time, before CLK↑ Data 3 2.5 2 1.5 ns
CLR inactive 0 0 0.5 0.5
th Hold time, data after CLK↑ 0 0 0.5 0.5 ns

6.7 Timing Requirements, –40°C to 125°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
–40°C to 125°C UNIT
VCC = 1.8 V
± 0.15 V		 VCC = 2.5 V
± 0.2 V		 VCC = 3.3 V
± 0.3 V		 VCC = 5 V
± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 100 125 150 175 MHz
tw Pulse duration CLR Low 5.6 3 2.8 2.5 ns
CLK High or low 3.5 3 2.8 2.5
tsu Setup time, before CLK↑ Data 3 2.5 2 1.5 ns
CLR inactive 0.5 0.5 0.7 0.7
th Hold time, data after CLK↑ 0.5 0.5 0.7 0.7 ns

6.8 Switching Characteristics, –40°C to 85°C

over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 2)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 –40°C to 85°C UNIT
VCC = 1.8 V
± 0.15 V		 VCC = 2.5 V
± 0.2 V		 VCC = 3.3 V
± 0.3 V		 VCC = 5 V
± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 100 125 150 175 MHz
tpd CLK Q 2.5 12.9 2 6.5 1.4 4.6 1 3 ns
CLR 2.5 12.4 2 6 1.2 4.3 1 3.2

6.9 Switching Characteristics, –40°C to 85°C

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 –40°C to 85°C UNIT
VCC = 1.8 V
± 0.15 V		 VCC = 2.5 V
± 0.2 V		 VCC = 3.3 V
± 0.3 V		 VCC = 5 V
± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 100 125 150 175 MHz
tpd CLK Q 2.7 13.4 2.2 7.1 1.6 5.7 1.5 4 ns
CLR 2.7 12.9 2.2 7 1.5 5.8 1.3 4.1

6.10 Switching Characteristics, –40°C to 125°C

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 –40°C to 125°C UNIT
VCC = 1.8 V
± 0.15 V		 VCC = 2.5 V
± 0.2 V		 VCC = 3.3 V
± 0.3 V		 VCC = 5 V
± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 100 125 150 175 MHz
tpd CLK Q 2.7 15.4 2.2 8.1 1.6 6.7 1.5 5 ns
CLR 2.7 14.9 2.2 8 1.5 6.8 1.3 5.1

6.11 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 18 19 19 21 pF

6.12 Typical Characteristics

SN74LVC1G175 C001_SCES650.pngFigure 1. Voltage vs Capacitance

7 Parameter Measurement Information

SN74LVC1G175 pmi_lvc_cl15.gifFigure 2. Load Circuit and Voltage Waveforms
SN74LVC1G175 pmi_lvc_cl3050.gifFigure 3. Load Circuit and Voltage Waveforms

 
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