SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset
1 Features
- Available in the Texas Instruments
NanoFree™ package - Supports 5-V VCC operation
- Inputs accept voltages to 5.5-V
- Supports down translation to VCC
- Maximum tpd of 5.9-ns at 3.3-V
- Low power consumption, 10-µA maximum ICC
- ±24-mA output drive at 3.3-V
- Typical VOLP (output ground bounce)
< 0.8-V at VCC = 3.3-V, TA = 25°C - Typical VOHV (output VOH
undershoot)
> 2-V at VCC = 3.3 V, TA = 25°C - Ioff supports live insertion, partial-power-down mode, and back-drive protection
- Latch-up performance exceeds 100 mA per JESD 78, class II
- ESD protection exceeds JESD 22
- 2000-V human-body model
- 200-V machine model
- 1000-V charged-device model
2 Applications
- Servers
- LED displays
- Network switch
- Telecom infrastructure
- Motor drivers
- I/O expanders
3 Description
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A low level at the preset ( PRE) or clear ( CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| PART NUMBER | PACKAGE (1) | BODY SIZE |
|---|---|---|
| SN74LVC1G74 | SM8 (8) | 2.95 mm × 2.80 mm |
| US8 (8) | 2.30 mm × 2.00 mm | |
| X2SON (8) | 1.40 mm × 1.00 mm | |
| UQFN (8) | 1.50 mm × 1.50 mm |
Simplified
Schematic4 Revision History
Changes from Revision F (April 2020) to Revision G (September 2021)
- Updated the numbering format for tables, figures, and cross-references throughout the documentGo
- Updated the Application and Information sectionGo
- Updated the Device Power Button Circuit figure Typical Power Button Circuit sectionGo
Changes from Revision E (Janurary 2015) to Revision F (April 2020)
- Match RSE pinout with signal namesGo
Changes from Revision D (January 2013) to Revision E (Janurary 2015)
- Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
- Deleted Ordering Information table.Go
- Updated Features Go
Changes from Revision C (November 2012) to Revision D (January 2013)
Changes from Revision B (March 2012) to Revision C (November 2012)
Changes from Revision A (November 2011) to Revision B (February 2012)
- Added SN74LVC1G74DCURG4 part number to ORDERING INFORMATION tableGo
