SN74LVC1G80 Single Positive-Edge-Triggered D-Type Flip-Flop

1 Features

• Available in the Texas Instruments
  NanoFree™ Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Supports Down Translation to V_CC
• Maximum t_pd of 4.2 ns at 3.3 V
• Low Power Consumption, 10-µA Maximum I_CC
• ±24-mA Output Drive at 3.3 V
• I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

2 Applications

• Test and Measurement
• Enterprise Switching
• Telecom Infrastructure
• Motor Drives

3 Description

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

1. TG - Transmission Gate

4 Revision History

Changes from R Revision (December 2013) to S Revision

• Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
• Added max junction temperature to the Recommended Operating Conditions table Go
• Added operating free-air temperature for YZP package to the Recommended Operating Conditions table Go
• Changed R_θJA value for DBV package from: 206°C/W to: 243.4°C/WGo
• Changed R_θJA value for DCK package from: 252°C/W to: 278.9°C/WGo
• Changed R_θJA value for YZP package from: 132°C/W to: 136.9°C/WGo

Changes from Q Revision (January 2007) to R Revision

• Updated document to new TI data sheet format.Go
• Removed Ordering Information table.Go
• Updated I_off in Features.Go
• Updated operating temperature range.Go
• Added ESD warning Go

5 Pin Configuration and Functions

YZP Package

5-Pin DSBGA

Bottom View

DCK Package

5-Pin SC70

Top View

DBV Package

5-Pin SOT-23

Top View