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  • SN74LVC3G17 Triple Schmitt-Trigger Buffer

    • SCES470F August   2003  – August 2015 SN74LVC3G17

      PRODUCTION DATA.  

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  • SN74LVC3G17 Triple Schmitt-Trigger Buffer
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Operating Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCU|8
  • YZP|8
  • DCT|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sces470f_oa
  • sces470f_pm
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DATA SHEET

SN74LVC3G17 Triple Schmitt-Trigger Buffer

1 Features

  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Maximum tpd of 5.4 ns at 3.3 V
  • Low Power Consumption, 10-μA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

2 Applications

  • AV Receivers
  • Audio Docks: Portable
  • Blu-ray® Players and Home Theater
  • MP3 Players/Recorders
  • Personal Digital Assistants (PDAs)
  • Power: Telecom/Server AC/DC Supply: Single Controller: Analog and Digital
  • Solid State Drives (SSDs): Client and Enterprise
  • TVs: LCD/Digital and High-Definition (HDTVs)
  • Tablets: Enterprise
  • Video Analytics: Server
  • Wireless Headsets, Keyboards, and Mice

3 Description

This triple Schmitt-trigger buffer is designed for
1.65-V to 5.5-V VCC operation.

The SN74LVC3G17 device contains three buffers and performs the Boolean function Y = A. The device functions as three independent buffers but, because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC3G17DCT SSOP (8) 2.95 mm × 2.80 mm
SN74LVC3G17DCU VSSOP (8) 2.30 mm × 2.00 mm
SN74LVC3G17YZP DSBGA (8) 1.91 mm × 0.91 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

SN74LVC3G17 logic_ces470.gif

4 Revision History

Changes from E Revision (November 2013) to F Revision

  • Added the Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
  • Moved Tstg to Absolute Maximum Ratings table.Go

Changes from D Revision (Feburary 2007) to E Revision

  • Updated document to new TI data sheet format.Go
  • Updated operating temperature range.Go

5 Pin Configuration and Functions

DCT Package
8-Pin SSOP
Top View
SN74LVC3G17 po_DCT_ces470.gif
DCU Package
8-Pin VSSOP
Top View
SN74LVC3G17 po_DCU_ces470.gif
YZP Package
8-Pin DSBGA
Bottom View
SN74LVC3G17 po_YZP_ces470.gif
See mechanical drawing for dimensions.

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
1A 1 I Input 1
1Y 7 O Output 1
2A 3 I Input 2
2Y 5 O Output 2
3A 6 I Input 3
3Y 2 O Output 3
GND 4 — Ground
VCC 8 — Power Pin

 
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