SLLS259J November   1996  – October 2016 SN75LVDS82

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics 
  8. 8 Parameter Measurement Information
    1. 8.1 Equivalent Input and Output Schematic Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 LVDS Input Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low Power Mode
      2. 9.4.2 Test Patterns
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Signal Connectivity
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Power Up Sequence
        3. 10.2.1.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Decoupling Capacitor Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 4:28 Data Channel Expansion at up to
    1904 Mbps Throughput
  • Suited for SVGA, XGA, or SXGA Display
    Data Transmission From Controller to
    Display With Very Low EMI
  • Four Data Channels and Clock Low-Voltage
    Differential Channels In and 28 Data and
    Clock Low-Voltage TTL Channels Out
  • Operates From a Single 3.3-V Supply With
    250 mW (Typical)
  • 5-V Tolerant SHTDN Input
  • Falling Clock-Edge-Triggered Outputs
  • Packaged in Thin Shrink Small-Outline
    Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Pixel Clock Frequency Range of 31 MHz to
    68 MHz
  • No External Components Required for PLL
  • Inputs Meet or Exceed the Requirements of
    ANSI EIA/TIA-644 Standard

2 Applications

  • Printers
  • Appliances With an LCD
  • Digital Cameras
  • Laptop and PC Displays Industrial PC, Laptop, and other Factory Automation Displays Patient Monitor and Medical Equipment Displays Projectors Weight Scales

3 Description

The SN75LVDS82 FlatLink™ receiver contains four serial-in, 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit.

These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS83B, over five balanced-pair conductors, and expansion to 28 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 for 21-bit transfers.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×) the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit-wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop (PLL) clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).

The SN75LVDS82 requires only five line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN75LVDS82 TSSOP (56) 14.00 mm × 6.10 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

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