The TAS2120 is a mono, digital input Class-D audio amplifier with an integrated Boost for higher power delivery in battery-operated systems.
Device is optimized to deliver best battery life for real-use cases of music playback and voice calls. Advanced efficiency optimization features like Y-bridge, and algorithms enable the device to produce best-in-class efficiency across all power regions of operation. The Class-D amplifier is capable of delivering 8.2W output powerusing integrated Class-H Boost.
TAS2120 device supports look-ahead algorithm based optimum boost voltage levels to match the output of audio signal. This provides all the power needed for peak output while significantly reducing the average power consumption.
Up to four devices can share a common bus via I2S/TDM + I2C interfaces. The device also supports five HW Control pins that can configure the device for the desired mode of operation.
PIN | Type(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BGND | 12 | P | Boost ground. Connect to PCB GND plane strongly with multiple vias. |
DREG | 26 | P | Digital core voltage regulator output. Bypass to GND with a capacitor. Do not connect to an external load. |
FSYNC | 8 | I | I2S word clock or TDM frame sync. |
GREG | 17 | P | High-side gate CP regulator output. Do not connect to an external load. |
GND | 22, 23, 25 | P | Connect to PCB GND plane. Strong connection to ground plane required through multiple vias. |
IOVDD | 5 | P | 1.8V or 3.3V Digital IO supply. Decouple to GND with capacitor. |
IRQZ | 6 | O | Open drain, active low interrupt pin. Pull up to IOVDD with resistor if optional internal pullup is not used. |
OUT_N | 19 | O | Class-D negative output. |
OUT_P | 20 | O | Class-D positive output. |
PGND | 21 | P | Class-D Power stage ground. Connect to PCB GND plane strongly through multiple vias. |
PVDD | 18 | P | Integrated boost output and Class-D power stage supply. |
SBCLK | 9 | I | I2S/TDM serial bit clock. |
SDIN | 10 | I | I2S or TDM serial data input. |
SDOUT | 11 | I/O | I2S or TDM serial data output. |
SDZ | 7 | I | Active low hardware shutdown. |
SEL1 | 16 | I | HW Mode: Select 1 Pin. Amplifier gain level selection with volume ramp enable and disable options. I2C Mode: Short to GND for I2C mode selection. |
SEL2_SCL | 4 | I | HW Mode: Select 2 Pin. I2S, TDM, Left justified selection. I2C Mode: Clock Pin. Pull up to IOVDD with a resistor. |
SEL3_SDA | 3 | I/O | HW Mode: Select 3 Pin. Data valid rising edge and falling edge selection. I2C Mode: Data Pin. Pull up to IOVDD with a resistor. |
SEL4_ADDR | 2 | I | HW Mode: Select 4 Pin.Y-bridge threshold configuration setting. I2C Mode: I2C address pin. |
SEL5 | 1 | I/O | HW Mode: Select5 Pin. Boost 1S, 2S, External PVDD mode selection. |
SW | 13 | P | Boost converter switch input. |
VBAT | 15 | P | Battery power supply input. Connect to a 2.5 to 5.5V supply and decouple with a capacitor. |
VBAT_SNS | 14 | I | Battery sense terminal. Connect to 1S or 2S battery supply for remote battery sensing. Ground the pin if remote sensing is not used. |
VDD | 24 | P | Connect to 1.8V supply and decouple to GND with capacitor. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage | PVDD | –0.3 | 19 | V |
Supply Voltage | VBAT | –0.3 | 6 | V |
Supply Voltage Sense | VBAT_SNS | –0.3 | 12 | V |
Supply Voltage | VDD | –0.3 | 2 | V |
Supply Voltage | IOVDD | –0.3 | 6 | V |
Boost Switching Pin | SW | –0.7 | 19 | V |
Class-D Output | OUTP, OUTM | –0.7 | 19 | V |
High Side Drive Regulator | GREG | –0.3 | PVDD + 6 | V |
Digital Supply Regulator | DREG | –0.3 | 1.65 | V |
Digital IO Pins | Digital pins referenced to IOVDD supply | –0.3 | 6 | V |
Tstg | Storage temperature | –65 | 150 | °C |