TAS5624A 150-W Stereo and 300-W Mono PurePath™ HD Digital Input Class-D Power Stage
- SLAS844A May 2012 – January 2016 TAS5624A
  
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DATA SHEET

TAS5624A 150-W Stereo and 300-W Mono PurePath™ HD Digital Input Class-D Power Stage

1 Features

PurePath™ HD Integrated Feedback Provides:
- 0.025% THD at 1 W into 4 Ω
- > 65-dB PSRR (No Input Signal)
- > 105-dB (A-Weighted) SNR
Preclipping Output for Control of a Class-G Power Supply
Reduced Heat Sink Size Due to Use of 40-mΩ Output MOSFET With > 90% Efficiency at Full Output Power
Output Power at 10% THD+N
- 150-W and 4-Ω BTL Stereo Configuration
- 300-W and 2-Ω PBTL Mono Configuration
Output Power at 10% THD+N
- 125-W and 4-Ω BTL Stereo Configuration
- 250-W and 2-Ω PBTL Mono Configuration
Click-Free and Pop-Free Start-Up
Error Reporting Self-Protected Design With UVP, Overtemperature, and Short-Circuit Protection
EMI-Compliant When Used With Recommended System Design
44-Pin HTSSOP (DDV) Package for Reduced Board Size

2 Applications

Blu-ray™ and DVD Receivers
High-Power Sound Bars
Powered Subwoofer and Active Speakers
Mini Combo Systems

3 Description

The TAS5624A device is a thermally-enhanced version of the class-D power amplifier based on the TAS5614A using large MOSFETs for improved power efficiency and a novel gate-drive scheme for reduced losses in idle and at low-output signals leading to reduced heat sink size.

The unique preclipping output signal can be used to control a Class-G power supply. This combined with the low idle loss and high power efficiency of the TAS5624A leads to industry leading levels of efficiency ensuring a super green system.

The TAS5624A uses constant voltage gain. The internally-matched gain resistors ensure a high power supply rejection ratio giving an output voltage only dependent on the audio input voltage and free from any power supply artifacts.

The high integration of the TAS5624A makes the amplifier easy to use; and, using TI’s reference schematics and PCB layouts leads to fast design in time. The TAS5624A is available in the space-saving, surface-mount 44-pin HTSSOP package.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TAS5624A	HTSSOP (44)	14.00 mm × 6.10 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Typical TAS5624A Application Block Diagram

4 Revision History

Changes from * Revision (May 2012) to A Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go

5 Device Comparison Table

FEATURES	TAS5624A	TAS5612A	TAS5612LA	TAS5614A	TAS5614LA	TAS5622A
Maximum Power to Single-Ended Load	75		65		75	65
Maximum Power to Bridge Tied Load	200	165	125	200	150	150
Maximum Power to Parallel Bridge Tied Load	400	250	250	300	300	300
Minimum Supported Single-Ended Load	2		2		2	2
Minimum Supported Bridge Tied Load	3	3	4	3	4	3
Minimum Supported Parallel Bridge Tied Load	1.5	2	2	2	2	2
Closed-Loop and Open-Loop	Closed	Closed	Closed	Closed	Closed	Closed
Maximum Speaker Outputs (#)	4	2	4	2	4	2
Input Type	PWM	PWM	PWM	PWM	PWM	PWM
Control Type	Hardware	Hardware	Hardware	Hardware	Hardware	Hardware

6 Pin Configuration and Functions

DDV Package

44-Pin HTSSOP

Top View

Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION⁽²⁾
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION⁽²⁾
AVDD	13	P	Internal voltage regulator, analog section
BST_A	44	P	Bootstrap pin, A-side
BST_B	43	P	Bootstrap pin, B-side
BST_C	24	P	Bootstrap pin, C-side
BST_D	23	P	Bootstrap pin, D-side
C_START	7	O	Start-up ramp
CLIP	18	O	Clipping warning; open-drain; active-low
DVDD	8	P	Internal voltage regulator, digital section
FAULT	16	O	Shutdown signal, open-drain; active-low
GND	9, 10, 11, 12, 25, 26, 33, 34, 41, 42	P	Ground
GVDD_AB	1	P	Gate-drive voltage supply; AB-side
GVDD_CD	22	P	Gate-drive voltage supply; CD-side
INPUT_A	5	I	PWM Input signal for half-bridge A
INPUT_B	6	I	PWM Input signal for half-bridge B
INPUT_C	14	I	PWM Input signal for half-bridge C
INPUT_D	15	I	PWM Input signal for half-bridge D
M1	19	I	Mode selection 1 (LSB)
M2	20	I	Mode selection 2
M3	21	I	Mode selection 3 (MSB)
OC_ADJ	3	O	Overcurrent threshold programming pin
OTW	17	O	Overtemperature warning; open-drain; active-low
OUT_A	39, 40	O	Output, half-bridge A
OUT_B	35	O	Output, half-bridge B
OUT_C	32	O	Output, half-bridge C
OUT_D	27, 28	O	Output, half-bridge D
PowerPAD™	—	P	Ground, connect to grounded heat sink
PVDD_AB	36, 37, 38	P	PVDD supply for half-bridge A and B
PVDD_CD	29, 30, 31	P	PVDD supply for half-bridge C and D
RESET	4	I	Device reset Input; active-low
VDD	2	P	Input power supply

(1) I = Input, O = Output, and P = Power

(2) Located on the top side of the device for convenient thermal coupling to the heat sink.

Mode Selection Pins

MODE PINS			PWM Input⁽¹⁾	OUTPUT CONFIGURATION	INPUT A	INPUT B	INPUT C	INPUT D	MODE
M3	M2	M1	PWM Input⁽¹⁾	OUTPUT CONFIGURATION	INPUT A	INPUT B	INPUT C	INPUT D	MODE
0	0	0	2N + 1	2 × BTL	PWMa	PWMb	PWMc	PWMd	AD Mode
0	0	1	1N + 1⁽²⁾	2 × BTL	PWMa	Unused	PWMc	Unused	AD Mode
0	1	0	2N + 1	2 × BTL	PWMa	PWMb	PWMc	PWMd	BD Mode
0	1	1	1N + 1⁽²⁾	1 × BTL + 2 × SE	PWMa	Unused	PWMc	PWMd	AD Mode
1	0	0	2N + 1	1 × PBTL	PWMa	PWMb	0	0	AD Mode
1	0	0	1N + 1⁽²⁾	1 × PBTL	PWMa	Unused	0	1	AD Mode
1	0	0	2N + 1	1 × PBTL	PWMa	PWMb	1	0	BD Mode
1	0	1	1N + 1	4 × SE⁽³⁾	PWMa	PWMb	PWMc	PWMd	AD Mode

(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.

(2) Using 1N interface in BTL and PBTL mode results in increased DC offset on the output terminals.

(3) The 4 × SE mode can be used as 1 × BTL + 2 × SE configuration by feeding a 2N PWM signal to either INPUT_AB or INPUT_CD for improved DC offset accuracy