The TAS5733L device is an efficient, digital-input audio amplifier for driving stereo speakers configured as a bridge tied load (BTL). In parallel bridge tied load (PBTL) in can produce higher power by driving the parallel outputs into a single lower impedance load. One serial data input allows processing of up to two discrete audio channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a wide range of input data and data rates. A fully programmable data path routes these channels to the internal speaker drivers.
The TAS5733L device is a slave-only device receiving all clocks from external sources. The TAS5733L device operates with a PWM carrier between a 384-kHz switching rate and a 288-kHz switching rate, depending on the input sample rate. Oversampling combined with a fourth-order noise shaper provides a flat noise floor and excellent dynamic range from 20 Hz to 20 kHz.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TAS5733L | HTSSOP (48) | 12.50 mm × 6.10 mm |
Changes from * Revision (March 2016) to A Revision
PIN | TYPE(2) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ADR/FAULT | 19 | DI/DO | Dual function terminal which sets the LSB of the I²C Address to 0 if pulled to GND, 1 if pulled to AVDD. Also, if configured to be a fault output by the methods described in the Fault Indication section, this terminal will be pulled low when an internal fault occurs. |
AGND | 35 | P | Ground reference for analog circuitry (NOTE: This terminal should be connected to the system ground) |
AMP_OUT_A | 6 | AO | Speaker amplifier outputs |
AMP_OUT_B | 2 | ||
3 | |||
AMP_OUT_C | 46 | ||
47 | |||
AMP_OUT_D | 43 | ||
AVDD | 18 | P | Power supply for internal analog circuitry |
AVDD_REF | 17 | P | Internal power supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry) |
AVDD_REG | 38 | P | Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry) |
BSTRP_A | 9 | P | Connection points to for the bootstrap capacitors, which are used to create a power supply for the gate drive for the high-side device |
BSTRP_B | 1 | ||
BSTRP_C | 48 | ||
BSTRP_D | 40 | ||
DGND | 34 | P | Ground reference for digital circuitry (NOTE: This terminal should be connected to the system ground) |
DVDD | 33 | P | Power supply for the internal digital circuitry |
DVDD_REG | 23 | P | Voltage regulator derived from DVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry) |
GVDD_REG | 39 | P | Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry) |
LRCLK | 25 | DI | Word select clock for the digital signal that is active on the input data line of the serial port |
MCLK | 20 | DI | Master clock used for internal clock tree and sub-circuit/state machine clocking |
NC(1) | 12 | P | Not connected inside the device (all "no connect" terminals should be connected to system ground) |
13 | |||
30 | |||
36 | |||
37 | |||
OSC_GND | 22 | P | Ground reference for oscillator circuitry (NOTE: These terminals should be connected to the system ground) |
OSC_RES | 21 | AO | Connection point for precision resistor used by internal oscillator circuit. Details for this resistor are shown in the Typical Applications section |
PBTL | 11 | DI | Places the power stage in BTL mode when pulled low, or in PBTL mode when pulled high |
PDN | 24 | DI | Places the device in power down when pulled low |
PGND | 4 | — | Ground reference for power device circuitry (NOTE: This terminal should be connected to the system ground) |
5 | |||
44 | |||
45 | |||
PLL_FLTM | 15 | AO | Negative connection point for the PLL loop filter components |
PLL_FLTP | 16 | AO | Positive connection point for the PLL loop filter components |
PLL_GND | 14 | P | Ground reference for PLL circuitry (NOTE: This terminal should be connected to the system ground) |
PVDD | 7 | P | Power supply for internal power circuitry |
8 | |||
41 | |||
42 | |||
RST | 31 | DI | Places the devices in reset when pulled low |
SCL | 29 | DI | I²C serial control port clock |
SCLK | 26 | DI | Bit clock for the digital signal that is active on the input data line of the serial data port |
SDA | 28 | DI/DO | I²C serial control port data |
SDIN | 27 | DI | Data line to the serial data port |
SSTIMER | 10 | AO | Connection point for the capacitor that is used by the ramp timing circuit, as described in the SSTIMER Pin Functionality section |
TEST | 32 | — | Used by TI for testing during device production (NOTE: This terminal should be connected to system ground) |
PowerPAD | — | P | Exposed metal pad on the underside of the device, which serves as an electrical connection point for ground as well as a heat conduction path from the device into the board (NOTE: This terminal should be connected to ground through a land pattern defined in the Mechanical Data section) |