The TDC1011 is a fully integrated analog front-end (AFE) for ultrasonic sensing measurements of liquid level, fluid identification/concentration, and proximity/ distance applications common in automotive, industrial, medical, and consumer markets. When paired with an MSP430/C2000 MCU, power, wireless, and source code, TI provides the complete ultrasonic sensing solution.
TI's Ultrasonic AFE offers programmability and flexibility to accommodate a wide-range of applications and end equipment. The TDC1011 can be configured for multiple transmit pulses and frequencies, gain, and signal thresholds for use with a wide-range of transducer frequencies (31.25kHz to 4MHz) and Q-factors. Similarly, the programmability of the receive path allows ultrasonic waves to be detected over a wider range of distances/tank sizes and through various mediums.
Selecting different modes of operation, the TDC1011 can be optimized for low power consumption, making it ideal for battery powered applications. The low noise amplifiers and comparators provide extremely low jitter, enabling picosecond resolution and accuracy.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TDC1011-Q1 | TSSOP (PW-28) | 9.70 mm × 4.40 mm |
DATE | REVISION | NOTES |
---|---|---|
July 2015 | * | Initial release. |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
NC | 1 | No Connect (leave floating) | |
RX | 2 | I | Receive input |
VCOM | 3 | P | Output common mode voltage bias |
LNAOUT | 4 | O | Low noise amplifier output (for ac decoupling capacitor) |
PGAIN | 5 | I | Programmable gain amplifier input |
PGAOUT | 6 | O | Programmable gain amplifier output |
COMPIN | 7 | I | Echo qualification and zero-crossing detector input |
RTD1 | 8 | O | Resistance temperature detector channel 1 |
RTD2 | 9 | O | Resistance temperature detector channel 2 |
RREF | 10 | O | Reference resistor for temperature measurement |
RES | 11 | I | Reserved (connect to GND) |
ERRB | 12 | O | Error flag (open drain) |
START | 13 | O | Start pulse output |
STOP | 14 | O | Stop pulse output |
EN | 15 | I | Enable (active high; when low the TDC1011 is in SLEEP mode) |
TRIGGER | 16 | I | Trigger input |
RESET | 17 | I | Reset (active high) |
SCLK | 18 | I | Serial clock for the SPI interface |
CSB | 19 | I | Chip select for the SPI interface (active low) |
SDI | 20 | I | Serial data input for the SPI interface |
SDO | 21 | O | Serial data output for the SPI interface |
VIO | 22 | P | Positive I/O supply |
VDD | 23, 24 | P | Positive supply; all VDD supply pins must be connected to the supply. Place a 100-nF bypass capacitor to ground in close proximity to the pin. |
CLKIN | 25 | I | Clock input |
GND | 26 | G | Negative supply |
NC | 27 | No Connect (leave floating) | |
TX | 28 | O | Transmit output |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Analog supply voltage, VDD pins | –0.3 | 6.0 | V |
VIO | I/O supply voltage (VIO must always be lower than or equal to VDD supply) | –0.3 | 6.0 | V |
VI | Voltage on any analog input pin(3) | –0.3 | VDD + 0.3 | V |
VI | Voltage on any digital input pin(3) | –0.3 | VIO + 0.3 | V |
II | Input current at any pin | 5 | mA | |
TJ | Operating junction temperature | –40 | 125 | °C |
Tstg | Storage temperature range | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC A100-002(1) | ±2000 | V | |
Charged-device model (CDM), per AEC Q100-011 | All pins | ±500 | |||
Corner pins (1, 14, 15 and 28) | ±750 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Analog supply voltage, VDD pins | 2.7 | 5.5 | V |
VIO | Digital supply voltage, (VIO must always be lower than or equal to VDD supply) | 1.8 | VDD | V |
VI | Voltage on any analog input pin | GND | VDD | V |
VI | Voltage on any digital input pin | GND | VIO | V |
ƒCLKIN | Operating frequency | 0.06 | 16 | MHz |
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC | TDC1011 TSSOP PW (28 PINS) |
UNIT | |
---|---|---|---|
RθJA | Junction-to-ambient thermal resistance | 83.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 29.9 | |
RθJB | Junction-to-board thermal resistance | 40.8 | |
ψJT | Junction-to-top characterization parameter | 2.4 | |
ψJB | Junction-to-board characterization parameter | 40.3 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
TRANSMITTER SIGNAL PATH (TX) | |||||||
VOUT(TX) | Output voltage swing | ƒout = 1 MHz, RL = 75 Ω to VCM | HIGH | VDD – 0.32 | V | ||
LOW | 0.32 | V | |||||
IOUT(TX) | Output drive current | ƒout = 1 MHz, RL = 75 Ω to VCM | 22 | mARMS | |||
ƒOUT(TX) | Output TX frequency | ƒCLKIN = 8 MHz, divide-by-2 (programmable; see Transmitter Signal Path) | 4 | MHz | |||
RECEIVER SIGNAL PATH (RX) | |||||||
ΔtSTOP | STOP cycle-to-cycle jitter | LNA capacitive feedback, GPGA = 6 dB, ƒIN = 1 MHz, VIN = 100 mVPP, CVCOM = 1 µF and Figure 14 | 50 | psRMS | |||
LNA | |||||||
GLNA | LNA gain | Capacitive feedback, CIN = 300 pF, ƒIN = 1 MHz, RL = 100 kΩ to VCM, CVCOM = 1 µF | 20 | dB | |||
enLNA | LNA input referred noise density | Capacitive feedback, CIN = 300 pF, ƒ = 1 MHz, VDD = 3.1 V, VIN = VCM, RL = ∞, CVCOM = 1 µF | 2 | nV/√Hz | |||
VIN(LNA) | Input voltage range | Resistive feedback, RL = 1 kΩ to VCM, CVCOM = 1 µF | HIGH | VCM + (VCM – 0.24) / (GLNA) | V | ||
LOW | VCM – (VCM – 0.24) / (GLNA) | V | |||||
VOUT(LNA) | Output voltage range | Resistive feedback, RL = 1 kΩ to VCM, CVCOM = 1 µF | HIGH | VDD – 0.24 | V | ||
LOW | GND + 0.24 | V | |||||
SRLNA | Slew rate(6) | Resistive feedback, RL = 1 kΩ to VCM, 100mV step, CVCOM = 1 µF | 9 | V/μs | |||
BWLNA | –3-dB bandwidth | Capacitive feedback, CIN = 300 pF, RL= 100 kΩ to VCM, CVCOM = 1 µF | 5 | MHz | |||
VOS(LNA) | LNA input offset voltage | Resistive mode, VIN = VCM, RL = ∞ | ±320 | µV | |||
VCOM | |||||||
VCOM | VCOM output voltage | CVCOM = 1 µF | VCM | V | |||
VCOM output error | 0.5% | ||||||
PGA | |||||||
VIN(PGA) | PGA input range | RL = 100 kΩ to VCM, CL = 10 pF to GND | HIGH | VCM + (VCM – 0.06) / (GPGA) | V | ||
LOW | VCM – (VCM – 0.06) / (GPGA) | V | |||||
GPGAMIN | PGA min gain | DC, RL = ∞, CL = 10 pF | 0 | dB | |||
GPGAMAX | PGA max gain | 21 | dB | ||||
ΔGPGA | PGA gain step size | 3 | dB | ||||
GE(PGA) | PGA gain error | DC, GPGA = 0 dB, RL = ∞, CL = 10 pF | 5% | ||||
TCGPGA | PGA gain temperature coefficient | DC, GPGA = 0 dB, RL = ∞, CL = 10 pF | 170 | ppm/°C | |||
enPGA | PGA input referred noise density | GPGA = 21 dB, ƒ = 1 MHz, VDD = 3.1V, VIN = VCM, RL = ∞, CVCOM = 1 µF | 3.1 | nV/√Hz | |||
VOUT(PGA) | Output range | RL = 100 kΩ to VCM, CL = 10 pF to GND | HIGH | VDD – 0.06 | V | ||
LOW | 60 | mV | |||||
BWPGA | –3-db bandwidth | GPGA = 21 dB, RL = 100 kΩ to VCM, CL = 10 pF, CVCOM = 1 µF | 5 | MHz | |||
SRPGA | Slew rate(6) | GPGA = 21 dB, RL = 100 kΩ to VCM, CL = 10 pF, CVCOM = 1 µF | 12.5 | V/µs | |||
ZERO CROSS COMPARATOR | |||||||
VOS(COMP) | Input offset voltage(5) | Referred to VCOM | ±115 | µV | |||
enCOMP | Zero crossing comparator input referred noise(5) | 1 MHz | 5 | nV/√Hz | |||
HYSTCOMP | Hysteresis (5) | Referred to VCOM | -10 | mV | |||
THRESHOLD DETECTOR | |||||||
VTHDET | Threshold level | ECHO_QUAL_THLD = 0h, VCOM referred | –35 | mV | |||
ECHO_QUAL_THLD = 7h, VCOM referred | –1.5 | V | |||||
TEMPERATURE SENSOR INTERFACE(1) | |||||||
TERROR | Temperature measurement accuracy | RREF = 1 kΩ, PT1000 range: –40 to 125°C(2) | 1 | °C | |||
RREF = 1 kΩ, PT1000 range: –15°C to 85°C(2) | 0.5 | °C | |||||
Relative accuracy | RREF = 1 kΩ, RRTD1 = RRTD2 = 1.1 kΩ | 0.02 | °CRMS | ||||
TGE | Gain error | 5.8 | m°C/°C | ||||
POWER SUPPLY | |||||||
IDD | VDD supply current | Sleep (EN = CLKIN = TRIGGER = low) | 0.61 | µA | |||
Continuous receive mode, LNA and PGA bypassed | 2.8 | 3 | mA | ||||
Continuous receive mode, LNA and PGA active | 6.2 | 7.5 | mA | ||||
Temp. measurement only (PT1000 mode)(3) | 370 | 400 | µA | ||||
Temp. measurement (PT500 mode)(4) | 500 | 540 | µA | ||||
IIO | VIO supply sleep current(5) | Sleep (EN = CLKIN = TRIGGER = low) | 2 | nA | |||
DIGITAL INPUT/OUTPUT CHARACTERISTICS | |||||||
VIL | Input logic low threshold | 0.2 × VIO | V | ||||
VIH | Input logic high threshold | 0.8 × VIO | V | ||||
VOL | Output logic low threshold | SDO pin, 100-μA current | 0.2 | V | |||
SDO pin, 1.85-mA current | 0.4 | V | |||||
START and STOP pins, 100-μA current | 0.5 | V | |||||
START and STOP pins, 1.85-mA current | 0.6 | V | |||||
ERRB pin, 100-μA current | 0.2 | V | |||||
ERRB pin, 1.85-mA current | 0.4 | V | |||||
VOH | Output logic high threshold | SDO pin, 100-μA current | VIO – 0.2 | V | |||
SDO pin, 1.85-mA current | VIO – 0.6 | V | |||||
START and STOP pins, 100-μA current | VIO – 0.5 | V | |||||
START and STOP pins, 1.85-mA current | VIO – 0.6 | V | |||||
ERRB pin, 0-µA current | VIO – 0.2 | V | |||||
IOMAX | Maximum output current for SDO, START and STOP | 1.85 | mA |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
ƒSCLK | Serial clock frequency | 26 | MHz | ||
t1 | High period, SCLK | 16 | ns | ||
t2 | Low period, SCLK | 16 | ns | ||
t3 | Set-up time, nCS to SCLK | 10 | ns | ||
t4 | Set-up time, SDI to SCLK | 12 | ns | ||
t5 | Hold time, SCLK to SDI | 12 | ns | ||
t6 | SCLK transition to SDO valid time | 16 | ns | ||
t7 | Hold time, SCLK transition to nCS rising edge | 10 | ns | ||
t8 | nCS inactive | 17 | ns | ||
t9 | Hold time, SCLK transition to nCS falling edge | 10 | ns | ||
tr / tf | Signal rise and fall times(1) | 1.8 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
START, STOP, ENABLE, RESET, CLOCKIN, TRIGGER, ERR | ||||||
PWSTART | Pulse width for START signal | TX_FREQ_DIV = 2h, NUM_TX = 1 | 1 | μs | ||
TX_FREQ_DIV = 2h, NUM_TX = 2 | 2 | μs | ||||
TX_FREQ_DIV = 2h, NUM_TX ≥ 3 | 3 | μs | ||||
tr / tf START | Rise/fall time for START signal | 20% to 80%, 20-pF load | 0.25 | ns | ||
tr / tf STOP | Rise/fall time for STOP signal | 20% to 80%, 20-pF load | 0.25 | ns | ||
ƒCLKIN | Maximum CLKIN input frequency | 16 | MHz | |||
tr / tf CLKIN | CLKIN input rise/fall time(1) | 20% to 80% | 10 | ns | ||
tr / tf TRIG | TRIGGER input rise/fall time(1) | 20% to 80% | 10 | ns | ||
tEN_TRIG | Enable to trigger wait time(1) | 50 | ns | |||
tRES_TRIG | Reset to trigger wait time(1) | TX_FREQ_DIV = 2h (see TX/RX Measurement Sequencing and Timing) | 3.05 | μs |
VDD = VIO = 3.7V | Capacitive Feedback Mode | RL = 1kΩ |
VDD = VIO = 3.1V | Capacitive Feedback Mode | RL = ∞ |
VDD = VIO = 3.7V | Resistive Feedback Mode | RL = 1kΩ |
VIN = 100mV | fIN = 100kHz | |
VDD = VIO = 3.7V | Capacitive Feedback Mode | RL = 100kΩ |
CIN = 300 pF |
VDD = VIO = 5V | LNA Capacitive Feedback Mode | PGA Gain of 6dB |
VIN = 100mV | fIN = 1MHz | |
(See Figure 14) | Count >= 10000 |
VDD = VIO = 3.7V | LNA Capacitive Feedback Mode | PGA Gain of 6dB |
VIN = 100mV | fIN = 1MHz | |
TA = -40C° | (See Figure 14) | Count >= 10000 |
VDD = VIO = 3.7V | Gain of 21dB | RL = 1kΩ |
VDD = VIO = 3.7V | Gain of 21dB | RL = ∞ |
VDD = VIO = 3.7V | Gain of 21dB | RL = 100kΩ |
VIN = 100mV | fIN = 100kHz | |
VDD = VIO = 3.7V | Gain of 21dB | RL = 100kΩ |
VDD = VIO = 3.7V | LNA Capacitive Feedback Mode | PGA Gain of 6dB |
VIN = 100mV | fIN = 1MHz | |
TA = 25C° | (See Figure 14) | Count >= 10000 |
VDD = VIO = 3.7V | LNA Capacitive Feedback Mode | PGA Gain of 6dB |
VIN = 100mV | fIN = 1MHz | |
TA = 125C° | (See Figure 14) | Count >= 10000 |