TLV07 36-V Precision, Rail-to-Rail Output Operational Amplifier
1 Features
- Low Offset Voltage: 100 µV (Maximum)
- Rail-to-Rail Output
- Low Noise: 19 nV / √Hz
- Unity-Gain Stable
- RFI Filtered Inputs
- Input Range Includes Negative Supply
- Rail-to-Rail Output
- Gain Bandwidth: 1 MHz
- Low Quiescent Current: 930 µA
- Full Industrial Temperature Range:
–40°C to +125°C - Offered in the Industry-Standard 8-Pin SOIC Package
2 Applications
- Battery Testers
- Tracking Amplifier in Power Modules
- Merchant Power Supplies
- Transducer Amplifiers
- Temperature Measurements
- Strain Gauge Amplifiers
3 Description
The TLV07 device is a 36-V, single-supply, low-noise, precision operational amplifier (op amp) manufactured using TI’s laser trim operational amplifier technology. Each amplifiers' input offset voltage is trimmed in production to obtain a low offset voltage of 100 µV (maximum).
The TLV07 offers outstanding dc precision and ac performance, including rail-to-rail output, low offset voltage (±100 µV, maximum) and 1-MHz bandwidth. The TLV07 is stable at G = 1 with capacitive loads up to 200 pF. The input can operate 100 mV below the negative rail and within 2 V of the positive rail. This wide input voltage range, combined with a high CMRR of 120 dB, make the TLV07 well-suited when operated in the non-inverting configuration.
The TLV07 op amp is specified from –40°C to +125°C.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TLV07 | SOIC (8) | 4.90 mm × 3.91 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
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Single Pole Low-Pass Filter With Gain
4 Revision History
Changes from * Revision (July 2017) to A Revision
- First release of production-data data sheet Go
5 Pin Configuration and Functions
Pin Functions: TLV07
| NAME | NO. | I/O | DESCRIPTION |
|---|---|---|---|
| –IN | 2 | I | Negative (inverting) input |
| +IN | 3 | I | Positive (non-inverting) input |
| NC | 1, 5, 8 | — | No internal connection (can be left floating) |
| OUT | 6 | O | Output |
| V+ | 7 | — | Positive (highest) power supply |
| V– | 4 | — | Negative (lowest) power supply |
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted.(1)| MIN | MAX | UNIT | |
|---|---|---|---|
| Supply voltage | –20 | 20 | V |
| Single supply voltage | 40 | V | |
| Signal input pin voltage | (V–) – 0.5 | (V+) + 0.5 | V |
| Signal input pin current | –10 | 10 | mA |
| Output short-circuit current(2) | Continuous | ||
| Operating ambient temperature, TA | –40 | 125 | °C |
| Junction temperature, TJ | 150 | °C | |
| Storage temperature, Tstg | –65 | 150 | °C |
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VS | Supply voltage (VS = V+ – V–) | 2.7 | 36 | V |
| TA | Operating temperature | –40 | 125 | °C |
6.4 Thermal Information: TLV07
| THERMAL METRIC | TLV07 | UNIT | |
|---|---|---|---|
| D (SOIC) | |||
| 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 149.5 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 97.9 | °C/W |
| RθJB | Junction-to-board thermal resistance | 87.7 | °C/W |
| ψJT | Junction-to-top characterization parameter | 35.5 | °C/W |
| ψJB | Junction-to-board characterization parameter | 89.5 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | °C/W |
6.5 Electrical Characteristics
at TA = 25°C, V+ = +15 V, V- = -15 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted).| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| OFFSET VOLTAGE | ||||||
| VOS | Input offset voltage | 50 | ±100 | µV | ||
| dVOS/dT | Input offset voltage drift | TA = –40°C to 125°C | ±0.9 | µV/°C | ||
| PSRR | Input offset voltage vs power supply | VS = 2.7 V to 36 V | 0.3 | µV/V | ||
| INPUT BIAS CURRENT | ||||||
| IB | Input bias current | ±40 | pA | |||
| TA = –40°C to 125°C | ±3 | nA | ||||
| IOS | Input offset current | ±4 | pA | |||
| NOISE | ||||||
| Input voltage noise | ƒ = 0.1 Hz to 10 Hz | 2.7 | µVPP | |||
| en | Input voltage noise density | ƒ = 1 kHz | 19 | nV/√Hz | ||
| INPUT VOLTAGE | ||||||
| VCM | Common-mode voltage range | (V–) – 0.1 | (V+) – 2 | V | ||
| CMRR | Common-mode rejection ratio | VS = ±18 V, (V–) - 0.1 V < VCM < (V+) – 2 V | 104 | 120 | dB | |
| INPUT IMPEDANCE | ||||||
| Differential | 100 || 3 | MΩ || pF | ||||
| Common-mode | 6 || 3 | 1012 Ω || pF | ||||
| OPEN-LOOP GAIN | ||||||
| AOL | Open-loop voltage gain | (V–) + 0.35 V < VO < (V+) – 0.35 V | 110 | 130 | dB | |
| FREQUENCY RESPONSE | ||||||
| GBP | Gain bandwidth product | 1 | MHz | |||
| SR | Slew rate | G = 1 | 0.4 | V/µs | ||
| tS | Settling time | To 0.1%, VS = ±18 V, G = +1, 10-V step | 20 | µs | ||
| To 0.01% (12-bit), VS = ±18 V G = 1 10-V step |
28 | µs | ||||
| OUTPUT | ||||||
| VO | Voltage output swing from rail | RL = 10 kΩ | 120 | mV | ||
| ISC | Short-circuit current | 17 | mA | |||
| RO | Open-loop output resistance | ƒ = 1 MHz IO = 0 A |
900 | Ω | ||
| POWER SUPPLY | ||||||
| IQ | Quiescent current per amplifier | IO = 0 A | 930 | 1800 | µA | |
| TEMPERATURE | ||||||
| Specified range | –40 | 125 | °C | |||
| Operating range | –40 | 125 | °C | |||
6.6 Typical Characteristics
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted)Table 1. Characteristic Performance Measurements
| DESCRIPTION | FIGURE |
|---|---|
| Offset Voltage Production Distribution | Figure 1 |
| Offset Voltage Drift Distribution | Figure 2 |
| Offset Voltage vs Temperature | Figure 3 |
| Offset Voltage vs Common-Mode Voltage | Figure 4 |
| Offset Voltage vs Power Supply | Figure 5 |
| IB and IOS vs Common-Mode Voltage | Figure 6 |
| Input Bias Current vs Temperature | Figure 7 |
| Output Voltage Swing vs Output Current (Maximum Supply) | Figure 8 |
| CMRR and PSRR vs Frequency (Referred-to-Input) | Figure 9 |
| CMRR vs Temperature | Figure 10 |
| PSRR vs Temperature | Figure 11 |
| 0.1-Hz to 10-Hz Noise | Figure 12 |
| Input Voltage Noise Spectral Density vs Frequency | Figure 13 |
| THD+N Ratio vs Frequency | Figure 14 |
| THD+N vs Output Amplitude | Figure 15 |
| Quiescent Current vs Temperature | Figure 16 |
| Quiescent Current vs Supply Voltage | Figure 17 |
| Open-Loop Gain and Phase vs Frequency | Figure 18 |
| Closed-Loop Gain vs Frequency | Figure 19 |
| Open-Loop Gain vs Temperature | Figure 20 |
| Open-Loop Output Impedance vs Frequency | Figure 21 |
| No Phase Reversal | Figure 22 |
| Positive Overload Recovery | Figure 23 |
| Negative Overload Recovery | Figure 24 |
| Small-Signal Step Response | Figure 25, Figure 26 |
| Large-Signal Step Response | Figure 27, Figure 28 |
| Large-Signal Settling Time | Figure 29 |
| Short-Circuit Current vs Temperature | Figure 30 |
| Maximum Output Voltage vs Frequency | Figure 31 |
| EMIRR IN+ vs Frequency | Figure 32 |
Figure 1. Input Offset Voltage Distribution
Figure 3. Input Offset Voltage vs Temperature
Figure 5. Offset Voltage vs Power Supply
Figure 7. Input Bias Current vs Temperature
Figure 9. CMRR and PSRR vs Frequency
Figure 11. PSRR vs Temperature
Figure 13. Input Voltage Noise Spectral Density vs Frequency
Figure 15. THD + N vs Output Amplitude
Figure 17. Quiescent Current vs Supply Voltage
Figure 19. Closed-Loop Gain vs Frequency
Figure 21. Open-Loop Output Impedance vs Frequency
Figure 23. Positive Overload Recovery
| G = +1 V/V |
| G = +1 V/V |
| 10-V positive step |
Figure 31. Maximum Output Voltage vs Frequency
Figure 2. Input Offset Voltage Drift Distribution
Figure 4. Input Offset Voltage vs Common-Mode Voltage
Figure 6. IB and IOS vs Common Mode Voltage
Figure 8. Output Voltage Swing vs Output Current (Maximum Supply)
Figure 10. CMRR vs Temperature
Figure 12. 0.1-Hz to 10-Hz Noise
Figure 14. THD + N Ratio vs Frequency
Figure 16. Quiescent Current vs Temperature
Figure 18. Open-Loop Gain and Phase vs Frequency
Figure 20. Open-Loop Gain vs Temperature
Figure 22. No Phase Reversal
Figure 24. Negative Overload Recovery
| G = –1 V/V |
| G = –1 V/V |
Figure 32. EMIRR IN+ vs Frequency
7 Detailed Description
7.1 Overview
The TLV07 operational amplifier provides high overall performance, making the device suitable for many general-purpose applications. The excellent offset drift of only 0.9 μV/°C provides excellent stability over the entire temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and AOL.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Operating Characteristics
The TLV07 op amp is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V). Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are shown in Typical Characteristics.
7.3.2 Phase-Reversal Protection
The TLV07 has an internal phase-reversal protection. Many operational amplifiers exhibit a phase reversal when the input drives beyond the linear common-mode range. This condition is most often encountered in noninverting circuits when the input drives beyond the specified common-mode voltage range, which causes the output to reverse into the opposite rail. The input of the TLV07 prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 33.
Figure 33. No Phase Reversal
7.3.3 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. The questions typically focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Internal electrostatic discharge (ESD) protection is built into the circuits to protect the circuits from accidental ESD events before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance of the circuitry to an electrical overstress event is helpful. Figure 34 shows the ESD circuits contained in the TLV07 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at the power-supply ESD cell, an absorption device, internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
Figure 34. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the TLV07, but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (see Figure 34), the ESD protection components are intended to remain inactive and do not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 34 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN sources current to the operational amplifier and becomes the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when the power supplies (V+ or V–) are at 0 V. This question depends on the supply characteristic when at 0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the supply pins; see Figure 34. Select the Zener voltage so that the diode does not turn on during normal operation. However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise above the safe-operating, supply-voltage level.
The TLV07 input pins are protected from excessive differential voltage with back-to-back diodes; see Figure 34. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, use an input series resistor to limit the input signal current.
7.4 Device Functional Modes
7.4.1 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from the saturated state to the linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds the rated operating voltage resulting from the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices must have time to return back to the normal state. After the charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. As a result, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time for the TLV07 is approximately 2 µs.
