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  • TLV62568 1-A High Efficiency Synchronous Buck Converter in SOT Package

    • SLVSD89B November   2016  – November 2017 TLV62568

      PRODUCTION DATA.  

  • CONTENTS
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  • TLV62568 1-A High Efficiency Synchronous Buck Converter in SOT Package
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode
      2. 7.3.2 100% Duty Cycle Low Dropout Operation
      3. 7.3.3 Soft Startup
      4. 7.3.4 Switch Current Limit
      5. 7.3.5 Under Voltage Lockout
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enabling/Disabling the Device
      2. 7.4.2 Power Good
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Output Filter Design
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Input and Output Capacitor Selection
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DDC|6
    • MPDS124I
  • DBV|5
    • MPDS018T
  • DRL|6
    • MPDS159I
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • slvsd89b_oa
  • slvsd89b_pm
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    • Full reading width
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DATA SHEET

TLV62568 1-A High Efficiency Synchronous Buck Converter in SOT Package

1 Features

  • Up to 95% Efficiency
  • Low RDS(ON) Switches 150 mΩ / 100 mΩ
  • 2.5-V to 5.5-V Input Voltage Range
  • Adjustable Output Voltage from 0.6 V to VIN
  • Power Save Mode for Light Load Efficiency
  • 100% Duty Cycle for Lowest Dropout
  • 35-µA Operating Quiescent Current
  • 1.5-MHz Switching Frequency
  • Power Good Output
  • Over Current Protection
  • Internal Soft Startup
  • Thermal Shutdown Protection
  • Available in SOT Package
  • Pin-to-Pin Compatible with TLV62569
  • Create a Custom Design Using the TLV62568 With the WEBENCH® Power Designer

2 Applications

  • General Purpose POL Supply
  • Network Video Camera
  • Set Top Box
  • Wireless Router

3 Description

The TLV62568 device is a synchronous step-down buck DC-DC converter optimized for high efficiency and compact solution size. The device integrates switches capable of delivering an output current up to 1 A.

At medium to heavy loads, the device operates in pulse width modulation (PWM) mode with 1.5-MHz switching frequency. At light load, the device automatically enters Power Save Mode (PSM) to maintain high efficiency over the entire load current range. In shutdown, the current consumption is reduced to less than 2 μA.

The TLV62568 provides an adjustable output voltage via an external resistor divider. An internal soft start circuit limits the inrush current during startup. Other features like over current protection, thermal shutdown protection and power good are built-in. The device is available in a SOT23 and SOT563 package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TLV62568 SOT-23 (5) 2.90 mm × 2.80 mm
TLV62568P SOT-23 (6)
TLV62568 SOT563 (6) 1.60 mm x 1.60 mm
TLV62568P SOT563 (6)
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Device Comparison

PART NUMBER FUNCTION PACKAGE MARKING
TLV62568DBV - 14VF
TLV62568PDDC Power Good 9X
TLV62568DRL - 18L
TLV62568PDRL Power Good 18N

SPACER

Simplified Schematic

TLV62568 TLV62568P typ_app_TLV62568P.gif

Efficiency at 5-V Input Voltage

TLV62568 TLV62568P D008_SLVSD89_TLV62568.gif

4 Revision History

Changes from A Revision (April 2017) to B Revision

  • Added WEBENCH links to data sheetGo
  • Changed TLV62568PDDC to production statusGo
  • Added DDC package thermal information.Go
  • Changed 1.2 V From: MIN value To: MAX value for High-level threshold at EN pinGo

Changes from * Revision (November 2016) to A Revision

  • Changed TLV62568DRL and TLV62568PDRL to production status.Go
  • Moved Device Comparison table to page 1 Go
  • Added DRL package thermal information.Go
  • Added startup time of TLV62568DRL, TLV62568PDRL Go
  • Added TLV62568PDRL layout.Go

5 Pin Configuration and Functions

TLV62568 TLV62568P All_Pinout_TLV62568.gif

Pin Functions

PIN NUMBER I/O/PWR DESCRIPTION
NAME SOT23-5 SOT23-6 SOT563-6
EN 1 1 5 I Device enable logic input. Logic high enables the device, logic low disables the device and turns it into shutdown. Do not leave floating.
GND 2 2 2 PWR Ground pin.
SW 3 3 4 PWR Switch pin connected to the internal FET switches and inductor terminal. Connect the inductor of the output filter to this pin.
VIN 4 4 3 PWR Power supply voltage input.
PG - 5 6 O Power good open drain output pin for TLV62568P. The pull-up resistor should not be connected to any voltage higher than 5.5V. If it's not used, leave the pin floating.
FB 5 6 1 I Feedback pin for the internal control loop. Connect this pin to an external feedback divider.
NC - - 6 O No connection pin for TLV62568DRL. The pin can be connected to the output. Or leave it floating.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage(2) VIN, EN, PG –0.3 6 V
SW (DC) –0.3 VIN+0.3 V
SW (AC, less than 10 ns)(3) –3.0 9 V
FB –0.3 5.5 V
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions(1)

MIN TYP MAX UNIT
VIN Input voltage 2.5 5.5 V
VOUT Output voltage 0.6 VIN V
IOUT Output current 1 A
TJ Operating junction temperature –40 125 °C
ISINK_PG Sink current at PG pin 1 mA
(1) Refer to the Application and Implementation section for further information.

6.4 Thermal Information

THERMAL METRIC(1) DBV
(5 Pins)		 DDC
(6 pins)		 DRL
(6 pins)		 UNIT
RθJA Junction-to-ambient thermal resistance 191.6 121.6 149.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 141.4 69.1 45.7 °C/W
RθJB Junction-to-board thermal resistance 44.5 45.5 31.1 °C/W
ψJT Junction-to-top characterization parameter 34.5 22.3 1.3 °C/W
ψJB Junction-to-board characterization parameter 43.9 46.0 31.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

VIN = 5 V, TJ = 25°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current into VIN pin Not switching 35 uA
ISD Shutdown current into VIN pin EN = 0 V 0.1 2 µA
VUVLO Under voltage lock out VIN falling 2.3 2.45 V
Under voltage lock out hysteresis 100 mV
TJSD Thermal shutdown threshold Junction temperature rising 150 °C
Junction temperature falling 130
LOGIC INTERFACE
VIH High-level threshold at EN pin 2.5 V ≤ VIN ≤ 5.5 V 0.95 1.2 V
VIL Low-level threshold at EN pin 2.5 V ≤ VIN ≤ 5.5 V 0.4 0.85 V
tSS Soft startup time TLV62568DBV 700 µs
TLV62568DRL, TLV62568PDRL, TLV62568PDDC 900
VPG Power good threshold, TLV62568P VFB rising, referenced to VFB nominal 95%
VFB falling, referenced to VFB nominal 90%
VPG,OL Power good low-level output voltage ISINK = 1 mA 0.4 V
IPG,LKG Input leakage current into PG pin VPG = 5 V 0.01 µA
tPG,DLY Power good delay time VFB falling 40 µs
OUTPUT
VFB Feedback regulation voltage 0.588 0.6 0.612 V
RDS(on) High-side FET on resistance 150 mΩ
Low-side FET on resistance 100
ILIM High-side FET current limit 1.5 A
fSW Switching frequency VOUT = 1.8 V 1.5 MHz

6.6 Typical Characteristics

TLV62568 TLV62568P D001_SLVSD89_TLV62568.gif
Figure 1. Quiescent Current vs Input Voltage
TLV62568 TLV62568P D003_SLVSD89_TLV62568.gif
1.
Figure 3. FB Voltage Accuracy
TLV62568 TLV62568P D002_SLVSD89_TLV62568.gif
1.
Figure 2. Shutdown Current vs Junction Temperature

7 Detailed Description

7.1 Overview

The TLV62568 is a high-efficiency synchronous step-down converter. The device operates with an adaptive off-time with peak current control scheme. The device operates at typically 1.5-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the required off time for the low-side MOSFET. It makes the switching frequency relatively constant regardless of the variation of input voltage, output voltage, and load current.

7.2 Functional Block Diagram

TLV62568 TLV62568P funct_block_TLV62568.gif Figure 4. TLV62568 Functional Block Diagram

7.3 Feature Description

7.3.1 Power Save Mode

The device automatically enters Power Save Mode to improve efficiency at light load when the inductor current becomes discontinuous. In Power Save Mode, the converter reduces switching frequency and minimizes current consumption. In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized by increasing the output capacitor.

7.3.2 100% Duty Cycle Low Dropout Operation

The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. In this mode, the high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input voltage to maintain output regulation, depending on the load current and output voltage, is calculated as:

Equation 1. VIN(MIN) = VOUT + IOUT x (RDS(ON) + RL)

where

  • RDS(ON) = High side FET on-resistance
  • RL = Inductor ohmic resistance (DCR)

7.3.3 Soft Startup

After enabling the device, internal soft startup circuitry ramps up the output voltage which reaches nominal output voltage during a startup time. This avoids excessive inrush current and creates a smooth output voltage rise slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal impedance.

The TLV62568 is able to start into a pre-biased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to its nominal value.

7.3.4 Switch Current Limit

The switch current limit prevents the device from high inductor current and drawing excessive current from a battery or input voltage rail. Excessive current might occur with a heavy load or shorted output circuit condition. The TLV62568 adopts the peak current control by sensing the current of the high-side switch. Once the high-side switch current limit is reached, the high-side switch is turned off and low-side switch is turned on to ramp down the inductor current with an adaptive off-time.

7.3.5 Under Voltage Lockout

To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down the device at voltages lower than VUVLO with VHYS_UVLO hysteresis.

7.3.6 Thermal Shutdown

The device enters thermal shutdown once the junction temperature exceeds the thermal shutdown rising threshold, TJSD. Once the junction temperature falls below the falling threshold, the device returns to normal operation automatically.

7.4 Device Functional Modes

7.4.1 Enabling/Disabling the Device

The device is enabled by setting the EN input to a logic High. Accordingly, a logic Low disables the device. If the device is enabled, the internal power stage starts switching and regulates the output voltage to the set point voltage. The EN input must be terminated and should not be left floating.

7.4.2 Power Good

The TLV62568P has a power good output. The PG pin goes high impedance once the output is above 95% of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage. The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pull-up resistor connecting to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used.

Table 1. PG Pin Logic

DEVICE CONDITIONS LOGIC STATUS
HIGH Z LOW
Enable EN = High, VFB ≥ VPG √
EN = High, VFB ≤ VPG √
Shutdown EN = Low √
Thermal Shutdown TJ > TJSD √
UVLO 1.4 V < VIN < VUVLO √
Power Supply Removal VIN ≤ 1.4 V √

 
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