The TMDS171 is a digital video interface (DVI) or high-definition multimedia interface (HDMI) retimer. The TMDS171 supports four TMDS channels, Audio Return Channel (SPDIF_IN/ARC_OUT), Hot Plug Detect (HPD) and Digital Display Control (DDC) interfaces. The TMDS171 supports signaling rates up to 3.4 Gbps to allow for the highest resolutions of 4k2k30p 24 bits per pixel and up to WUXGA 12-bit color depth or 1080p with higher refresh rates. The TMDS171 automatically configures itself as a re-driver at low data rate (< 1 Gbps) or as a re-timer above this data rate.
The TMDS171 supports dual power supply rails of 1.2 V on VDD and 3.3 V on VCC for active power reduction. Several methods of power management are implemented to reduce overall power consumption. TMDS171 supports fixed EQ gain or adaptive EQ control by I2C or pin strap to compensate for different lengths input cable or board traces.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TMDS171 | (VQFN) 48 Pins | 7.00 mm x 7.00 mm |
TMDS171I |
Simplified Schematic![]() |
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Changes from D Revision (August 2016) to E Revision
Changes from C Revision (April 2016) to D Revision
Changes from B Revision (February 2016) to C Revision
Changes from A Revision (December 2015) to B Revision
Changes from * Revision (October 2015) to A Revision
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
VCC | 13, 43 | P | 3.3 V Power Supply |
VDD | 14, 23, 24, 37, 48 | P | 1.2 V Power Supply |
GND | 7, 19, 41, 30 | G | Ground |
Thermal Pad | G | Ground | |
MAIN LINK INPUT PINS (FAIL SAFE) | |||
IN_D2p/n | 2, 3 | I | Channel 2 Differential Input |
IN_D1p/n | 5, 6 | I | Channel 1 Differential Input |
IN_D0p/n | 8, 9 | I | Channel 0 Differential Input |
IN_CLKp/n | 11, 12 | I | Clock Differential Input |
MAIN LINK OUTPUT PINS (FAIL SAFE) | |||
OUT_D2n/p | 34, 35 | O | TMDS Data 2 Differential Output |
OUT_D1n/p | 31, 32 | O | TMDS Data 1 Differential Output |
OUT_D0n/p | 28, 29 | O | TMDS Data 0 Differential Output |
OUT_CLKn/p | 25, 26 | O | TMDS Clock Differential Output |
HOT PLUG DETECT PINS | |||
HPD_SRC | 4 | O | Hot Plug Detect Output to source side |
HPD_SNK | 33 | I | Hot Plug Detect Input from sink side |
AUDIO RETURN CHANNEL and DDC PINS | |||
SPDIF_IN | 45 | I | SPDIF signal input |
ARC_OUT | 44 | O | Audio return channel output |
SDA_SRC | 47 | I/O | Source Side TMDS Port Bidirectional DDC Data line |
SCL_SRC | 46 | I/O | Source Side TMDS Port Bidirectional DDC Clock line |
SDA_SNK, | 39 | I/O | Sink Side TMDS Port Bidirectional DDC Data Line |
SCL_SNK | 38 | I/O | Sink Side TMDS Port Bidirectional DDC Clock Line |
CONTROL PINS(2) | |||
OE | 42 | I | Operation Enable/Reset Pin OE = L: Power Down Mode OE = H: Normal Operation Internal weak pull up: Resets device when transitions from H to L |
SIG_EN | 17 | I | Signal detector circuit enable SIG_EN = L: Signal Detect Circuit Disabled: Term resistors always connected (Default) SIG_EN = H: Signal Detect Circuit Enabled: When no valid clock device enters Standby Mode. Internal weak pull down |
PRE_SEL | 20 | I 3-Level |
De-emphasis Control when I2C_EN/PIN = Low. PRE_SEL = L: -2 dB PRE_SEL = No Connect: 0 dB PRE_SEL = H: Reserved When I2C_EN/PIN = High; De-emphasis is controlled through I2C |
EQ_SEL/A0 | 21 | I | Input Receive Equalization pin strap when I2C_EN/PIN = Low EQ_SEL = L: Fixed EQ at 7.5 dB EQ_SEL = No Connect: Adaptive EQ EQ_SEL = H: Fixed at 14 dB When I2C_EN/PIN = High Address Bit 1 Note: 3 level for pin strap programming but 2 level when I2C address |
I2C_EN/PIN | 10 | I | I2C_EN/PIN = High; Puts Device into I2C Control Mode I2C_EN/PIN = Low; Puts Device into Pin Strap Mode |
SCL_CTL | 15 | I/O | I2C Clock Signal when I2C_EN/PIN = High. Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be changed by I2C |
SDA_CTL | 16 | I/O | I2C Data Signal when I2C_EN/PIN = High Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be changed by I2C |
VSadj | 22 | I | TMDS Output Voltage Swing Control; Nominal 7.06 kΩ Resistor to GND |
A1 | 27 | I | High address bit 2 for I2C programming Weak internal pull down. Note: When I2C_EN/PIN = Low for Pin Strapping Mode leave this pin as No connect |
TX_TERM_CTL | 36 | I 3-Level |
Transmit Termination Control TX_TERM_CTL = H: No transmit Termination TX_TERM_CTL = L: Reserved TX_TERM_CTL = No Connect: Automatically selects the termination impedance 2 Gbps > DR ≤ 3.4 Gbps – 150 - 300 Ω differential near end termination DR < 2 Gbps – no termination Note: If left floating; the device will be in Automatic Select Mode. DR stands for Data Rate |
SWAP/POL | 1 | I 3-Level |
Receive Polarity Swap and Receive Lane Swap control pin SWAP/POL = H: Receive Lanes Polarity Swap (Retimer Mode Only) SWAP/POL = L: Receive Lanes (Retimer and Redriver Mode) Swap SWAP/POL = No Connect, Normal Operation |
NC | 18, 40 | – | No connect |