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DATA SHEET
TMS320F28004x Real-Time Microcontrollers
1 Features
- TMS320C28x 32-bit CPU
- 100 MHz
- IEEE 754 single-precision
Floating-Point Unit (FPU)
- Trigonometric Math Unit
(TMU)
- 3×-cycle to
4×-cycle improvement for common trigonometric functions versus
software libraries
- 13-cycle Park
transform
- Viterbi/Complex Math Unit
(VCU-I)
- Ten hardware breakpoints
(with ERAD)
- Programmable Control Law
Accelerator (CLA)
- 100 MHz
- IEEE 754 single-precision
floating-point instructions
- Executes code
independently of main CPU
- On-chip memory
- 256KB (128KW) of flash
(ECC-protected) across two independent banks
- 100KB (50KW) of RAM
(ECC-protected or parity-protected)
- Dual-zone security
supporting third-party development
- Unique Identification
(UID) number
- Clock and system control
- Two internal zero-pin
10-MHz oscillators
- On-chip crystal
oscillator and external clock input
- Windowed watchdog timer
module
- Missing clock detection
circuitry
- 1.2-V core, 3.3-V I/O design
- Internal VREG or DC-DC
for 1.2-V generation allows for single-supply designs
- Brownout reset (BOR)
circuit
- System peripherals
- 6-channel Direct Memory
Access (DMA) controller
- 40 individually
programmable multiplexed General-Purpose Input/Output (GPIO) pins
- 21 digital inputs on analog pins
- Enhanced Peripheral
Interrupt Expansion (ePIE) module
- Multiple low-power mode
(LPM) support with external wakeup
- Embedded Real-time
Analysis and Diagnostic (ERAD)
- Communications peripherals
- One Power-Management Bus
(PMBus) interface
- One Inter-integrated
Circuit (I2C) interface
(pin-bootable)
- Two Controller Area
Network (CAN) bus ports (pin-bootable)
- Two Serial Peripheral
Interface (SPI) ports
(pin-bootable)
- Two UART-Compatible
Serial Communication Interfaces (SCIs) (pin-bootable)
- One UART-Compatible Local
Interconnect Network (LIN)
- One Fast Serial Interface
(FSI) with a transmitter and receiver
- Analog system
- Three 3.45-MSPS, 12-bit
Analog-to-Digital Converters (ADCs)
- Up to 21 external channels
- Four integrated post-processing blocks (PPBs)
per ADC
- Seven windowed
comparators (CMPSS) with
12-bit reference
Digital-to-Analog Converters (DACs)
- Two 12-bit buffered DAC
outputs
- Seven Programmable Gain
Amplifiers (PGAs)
- Programmable gain settings: 3, 6, 12, 24
- Programmable output filtering
- Enhanced control peripherals
- 16 ePWM channels with
high-resolution capability (150-ps resolution)
- Integrated
dead-band support with high resolution
- Integrated
hardware trip zones (TZs)
- Seven Enhanced Capture
(eCAP) modules
- High-resolution
Capture (HRCAP) available on two modules
- Two Enhanced Quadrature
Encoder Pulse (eQEP) modules with support for CW/CCW operation
modes
- Four Sigma-Delta Filter
Module (SDFM) input channels (two parallel filters per channel)
- Standard SDFM
data filtering
- Comparator filter
for fast action for
overvalue or
undervalue condition
- Configurable Logic Block (CLB)
- Augments existing
peripheral capability
- Supports position manager
solutions
- InstaSPIN-FOC™
- Sensorless field-oriented
control (FOC) with FAST™ software
encoder
- Library in on-chip ROM
memory
- Functional Safety-Compliant
- Developed for functional safety applications
- Documentation available to aid ISO 26262 and IEC 61508 system
design
- Systematic capability up to ASIL D and SIL 3
- Hardware integrity up to
ASIL B
- Safety-related certification
- Package options:
- 100-pin Low-profile Quad
Flatpack (LQFP)
[PZ suffix]
- 64-pin LQFP [PM
suffix]
- 56-pin Very Thin Quad
Flatpack No-lead (VQFN) [RSH suffix]
- Temperature options:
- S: –40°C to 125°C
junction
- Q: –40°C to 125°C
free-air
(AEC Q100 qualification for
automotive applications)
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