The Delfino™ TMS320F28377D-EP is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-loop control applications such as industrial drives and servo motor control; solar inverters and converters; digital power; transportation; and power line communications. Complete development packages for digital power and industrial drives are available as part of the powerSUITE and DesignDRIVE initiatives. While the Delfino product line is not new to the TMS320C2000™ portfolio, the F28377D supports a new dual-core C28x architecture that significantly boosts system performance. The integrated analog and control peripherals also let designers consolidate control architectures and eliminate multiprocessor use in high-end systems.
The dual real-time control subsystems are based on TI’s 32-bit C28x floating-point CPUs, which provide 200 MHz of signal processing performance in each core. The C28x CPUs are further boosted by the new TMU accelerator, which enables fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations; and the VCU accelerator, which reduces the time for complex math operations common in encoded applications.
The F28377D microcontroller features two CLA real-time control coprocessors. The CLA is an independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can effectively double the computational performance of a real-time control system. By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and diagnostics. The dual C28x+CLA architecture enables intelligent partitioning between various system tasks. For example, one C28x+CLA core can be used to track speed and position, while the other C28x+CLA core can be used to control torque and current loops.
The TMS320F28377D-EP supports 1MB (512KW) of onboard flash memory with error correction code (ECC) and 204KB (102KW) of SRAM. Two 128-bit secure zones are also available on each CPU for code protection.
Performance analog and control peripherals are also integrated on the F28377D MCU to further enable system consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs, eQEPs, and other peripherals.
Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend the connectivity of the F28377D. The uPP interface is a new feature of the C2000™ MCUs and supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application.
PART NUMBER | PACKAGE | BODY SIZE |
---|---|---|
TMS320F28377D-EP | nFBGA (337) | 16.0 mm × 16.0 mm |
HLQFP (176) | 24.0 mm × 24.0 mm |
Figure 1-1 shows the CPU system and associated peripherals.
DATE | REVISION | NOTES |
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December 2017 | * | Initial Release |
Figure 3-1 to Figure 3-4 show the terminal assignments on the 337-ball ZWT New Fine Pitch Ball Grid Array. Each figure shows a quadrant of the terminal assignments. Figure 3-5 shows the pin assignments on the 176-pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack.
NOTE
The exposed lead frame die pad of the PowerPAD™ package serves two functions: to remove heat from the die and to provide ground path for the digital ground (analog ground is provided through dedicated pins). Thus, the PowerPAD should be soldered to the ground (GND) plane of the PCB because this will provide both the digital ground path and good thermal conduction path. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be designed with this technology in mind. A thermal land is required on the surface of the PCB directly underneath the body of the PowerPAD. The thermal land should be soldered to the exposed lead frame die pad of the PowerPAD package; the thermal land should be as large as needed to dissipate the required heat. An array of thermal vias should be used to connect the thermal pad to the internal GND plane of the board. See PowerPAD™ Thermally Enhanced Package for more details on using the PowerPAD package.
NOTE
PCB footprints and schematic symbols are available for download in a vendor-neutral format, which can be exported to the leading EDA CAD/CAE design tools. See the CAD/CAE Symbols section in the product folder for each device, under the Packaging section. These footprints and symbols can also be searched for at http://webench.ti.com/cad/.
Table 3-1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups are not enabled at reset.
TERMINAL | I/O/Z(1) | DESCRIPTION | ||||
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NAME | MUX POSITION | ZWT BALL NO. |
PTP PIN NO. |
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ADC, DAC, AND COMPARATOR SIGNALS | ||||||
VREFHIA | V1 | 37 | I | ADC-A high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIA and VREFLOA pins. NOTE: Do not load this pin externally. |
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VREFHIB | W5 | 53 | I | ADC-B high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIB and VREFLOB pins. NOTE: Do not load this pin externally. |
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VREFHIC | R1 | 35 | I | ADC-C high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIC and VREFLOC pins. NOTE: Do not load this pin externally. |
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VREFHID | V5 | 55 | I | ADC-D high reference. This voltage must be driven into the pin from external circuitry. Place at least a 1-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHID and VREFLOD pins. NOTE: Do not load this pin externally. |
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VREFLOA | R2 | 33 | I | ADC-A low reference. On the PZP package, pin 17 is double-bonded to VSSA and VREFLOA. On the PZP package, pin 17 must be connected to VSSA on the system board. |
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VREFLOB | V6 | 50 | I | ADC-B low reference | ||
VREFLOC | P2 | 32 | I | ADC-C low reference | ||
VREFLOD | W6 | 51 | I | ADC-D low reference | ||
ADCIN14 | T4 | 44 | I | Input 14 to all ADCs. This pin can be used as a general-purpose ADCIN pin or it can be used to calibrate all ADCs together (either single-ended or differential) from an external reference. | ||
CMPIN4P | I | Comparator 4 positive input | ||||
ADCIN15 | U4 | 45 | I | Input 15 to all ADCs. This pin can be used as a general-purpose ADCIN pin or it can be used to calibrate all ADCs together (either single-ended or differential) from an external reference. | ||
CMPIN4N | I | Comparator 4 negative input | ||||
ADCINA0 | U1 | 43 | I | ADC-A input 0. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled. | ||
DACOUTA | O | DAC-A output | ||||
ADCINA1 | T1 | 42 | I | ADC-A input 1. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled. | ||
DACOUTB | O | DAC-B output | ||||
ADCINA2 | U2 | 41 | I | ADC-A input 2 | ||
CMPIN1P | I | Comparator 1 positive input | ||||
ADCINA3 | T2 | 40 | I | ADC-A input 3 | ||
CMPIN1N | I | Comparator 1 negative input | ||||
ADCINA4 | U3 | 39 | I | ADC-A input 4 | ||
CMPIN2P | I | Comparator 2 positive input | ||||
ADCINA5 | T3 | 38 | I | ADC-A input 5 | ||
CMPIN2N | I | Comparator 2 negative input | ||||
ADCINB0 | V2 | 46 | I | ADC-B input 0. There is a 100-pF capacitor to VSSA on this pin in both ADC input or DAC reference mode which cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin. | ||
VDAC | I | Optional external reference voltage for on-chip DACs. There is a 100-pF capacitor to VSSA on this pin in both ADC input or DAC reference mode which cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin. | ||||
ADCINB1 | W2 | 47 | I | ADC-B input 1. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled. | ||
DACOUTC | O | DAC-C output | ||||
ADCINB2 | V3 | 48 | I | ADC-B input 2 | ||
CMPIN3P | I | Comparator 3 positive input | ||||
ADCINB3 | W3 | 49 | I | ADC-B input 3 | ||
CMPIN3N | I | Comparator 3 negative input | ||||
ADCINB4 | V4 | – | I | ADC-B input 4 | ||
ADCINB5 | W4 | – | I | ADC-B input 5 | ||
ADCINC2 | R3 | 31 | I | ADC-C input 2 | ||
CMPIN6P | I | Comparator 6 positive input | ||||
ADCINC3 | P3 | 30 | I | ADC-C input 3 | ||
CMPIN6N | I | Comparator 6 negative input | ||||
ADCINC4 | R4 | 29 | I | ADC-C input 4 | ||
CMPIN5P | I | Comparator 5 positive input | ||||
ADCINC5 | P4 | – | I | ADC-C input 5 | ||
CMPIN5N | I | Comparator 5 negative input | ||||
ADCIND0 | T5 | 56 | I | ADC-D input 0 | ||
CMPIN7P | I | Comparator 7 positive input | ||||
ADCIND1 | U5 | 57 | I | ADC-D input 1 | ||
CMPIN7N | I | Comparator 7 negative input | ||||
ADCIND2 | T6 | 58 | I | ADC-D input 2 | ||
CMPIN8P | I | Comparator 8 positive input | ||||
ADCIND3 | U6 | 59 | I | ADC-D input 3 | ||
CMPIN8N | I | Comparator 8 negative input | ||||
ADCIND4 | T7 | 60 | I | ADC-D input 4 | ||
ADCIND5 | U7 | — | I | ADC-D input 5 | ||
GPIO AND PERIPHERAL SIGNALS | ||||||
GPIO0 | 0, 4, 8, 12 | C8 | 160 | I/O | General-purpose input/output 0 | |
EPWM1A | 1 | O | Enhanced PWM1 output A (HRPWM-capable) | |||
SDAA | 6 | I/OD | I2C-A data open-drain bidirectional port | |||
GPIO1 | 0, 4, 8, 12 | D8 | 161 | I/O | General-purpose input/output 1 | |
EPWM1B | 1 | O | Enhanced PWM1 output B (HRPWM-capable) | |||
MFSRB | 3 | I/O | McBSP-B receive frame synch | |||
SCLA | 6 | I/OD | I2C-A clock open-drain bidirectional port | |||
GPIO2 | 0, 4, 8, 12 | A7 | 162 | I/O | General-purpose input/output 2 | |
EPWM2A | 1 | O | Enhanced PWM2 output A (HRPWM-capable) | |||
OUTPUTXBAR1 | 5 | O | Output 1 of the output XBAR | |||
SDAB | 6 | I/OD | I2C-B data open-drain bidirectional port | |||
GPIO3 | 0, 4, 8, 12 | B7 | 163 | I/O | General-purpose input/output 3 | |
EPWM2B | 1 | O | Enhanced PWM2 output B (HRPWM-capable) | |||
OUTPUTXBAR2 | 2 | O | Output 2 of the output XBAR | |||
MCLKRB | 3 | I/O | McBSP-B receive clock | |||
OUTPUTXBAR2 | 5 | O | Output 2 of the output XBAR | |||
SCLB | 6 | I/OD | I2C-B clock open-drain bidirectional port | |||
GPIO4 | 0, 4, 8, 12 | C7 | 164 | I/O | General-purpose input/output 4 | |
EPWM3A | 1 | O | Enhanced PWM3 output A (HRPWM-capable) | |||
OUTPUTXBAR3 | 5 | O | Output 3 of the output XBAR | |||
CANTXA | 6 | O | CAN-A transmit | |||
GPIO5 | 0, 4, 8, 12 | D7 | 165 | I/O | General-purpose input/output 5 | |
EPWM3B | 1 | O | Enhanced PWM3 output B (HRPWM-capable) | |||
MFSRA | 2 | I/O | McBSP-A receive frame synch | |||
OUTPUTXBAR3 | 3 | O | Output 3 of the output XBAR | |||
CANRXA | 6 | I | CAN-A receive | |||
GPIO6 | 0, 4, 8, 12 | A6 | 166 | I/O | General-purpose input/output 6 | |
EPWM4A | 1 | O | Enhanced PWM4 output A (HRPWM-capable) | |||
OUTPUTXBAR4 | 2 | O | Output 4 of the output XBAR | |||
EXTSYNCOUT | 3 | O | External ePWM synch pulse output | |||
EQEP3A | 5 | I | Enhanced QEP3 input A | |||
CANTXB | 6 | O | CAN-B transmit | |||
GPIO7 | 0, 4, 8, 12 | B6 | 167 | I/O | General-purpose input/output 7 | |
EPWM4B | 1 | O | Enhanced PWM4 output B (HRPWM-capable) | |||
MCLKRA | 2 | I/O | McBSP-A receive clock | |||
OUTPUTXBAR5 | 3 | O | Output 5 of the output XBAR | |||
EQEP3B | 5 | I | Enhanced QEP3 input B | |||
CANRXB | 6 | I | CAN-B receive | |||
GPIO8 | 0, 4, 8, 12 | G2 | 18 | I/O | General-purpose input/output 8 | |
EPWM5A | 1 | O | Enhanced PWM5 output A (HRPWM-capable) | |||
CANTXB | 2 | O | CAN-B transmit | |||
ADCSOCAO | 3 | O | ADC start-of-conversion A output for external ADC | |||
EQEP3S | 5 | I/O | Enhanced QEP3 strobe | |||
SCITXDA | 6 | O | SCI-A transmit data | |||
GPIO9 | 0, 4, 8, 12 | G3 | 19 | I/O | General-purpose input/output 9 | |
EPWM5B | 1 | O | Enhanced PWM5 output B (HRPWM-capable) | |||
SCITXDB | 2 | O | SCI-B transmit data | |||
OUTPUTXBAR6 | 3 | O | Output 6 of the output XBAR | |||
EQEP3I | 5 | I/O | Enhanced QEP3 index | |||
SCIRXDA | 6 | I | SCI-A receive data | |||
GPIO10 | 0, 4, 8, 12 | B2 | 1 | I/O | General-purpose input/output 10 | |
EPWM6A | 1 | O | Enhanced PWM6 output A (HRPWM-capable) | |||
CANRXB | 2 | I | CAN-B receive | |||
ADCSOCBO | 3 | O | ADC start-of-conversion B output for external ADC | |||
EQEP1A | 5 | I | Enhanced QEP1 input A | |||
SCITXDB | 6 | O | SCI-B transmit data | |||
UPP-WAIT | 15 | I/O | Universal parallel port wait. Receiver asserts to request a pause in transfer. | |||
GPIO11 | 0, 4, 8, 12 | C1 | 2 | I/O | General-purpose input/output 11 | |
EPWM6B | 1 | O | Enhanced PWM6 output B (HRPWM-capable) | |||
SCIRXDB | 2, 6 | I | SCI-B receive data | |||
OUTPUTXBAR7 | 3 | O | Output 7 of the output XBAR | |||
EQEP1B | 5 | I | Enhanced QEP1 input B | |||
UPP-START | 15 | I/O | Universal parallel port start. Transmitter asserts at start of DMA line. | |||
GPIO12 | 0, 4, 8, 12 | C2 | 4 | I/O | General-purpose input/output 12 | |
EPWM7A | 1 | O | Enhanced PWM7 output A (HRPWM-capable) | |||
CANTXB | 2 | O | CAN-B transmit | |||
MDXB | 3 | O | McBSP-B transmit serial data | |||
EQEP1S | 5 | I/O | Enhanced QEP1 strobe | |||
SCITXDC | 6 | O | SCI-C transmit data | |||
UPP-ENA | 15 | I/O | Universal parallel port enable. Transmitter asserts while data bus is active. | |||
GPIO13 | 0, 4, 8, 12 | D1 | 5 | I/O | General-purpose input/output 13 | |
EPWM7B | 1 | O | Enhanced PWM7 output B (HRPWM-capable) | |||
CANRXB | 2 | I | CAN-B receive | |||
MDRB | 3 | I | McBSP-B receive serial data | |||
EQEP1I | 5 | I/O | Enhanced QEP1 index | |||
SCIRXDC | 6 | I | SCI-C receive data | |||
UPP-D7 | 15 | I/O | Universal parallel port data line 7 | |||
GPIO14 | 0, 4, 8, 12 | D2 | 6 | I/O | General-purpose input/output 14 | |
EPWM8A | 1 | O | Enhanced PWM8 output A (HRPWM-capable) | |||
SCITXDB | 2 | O | SCI-B transmit data | |||
MCLKXB | 3 | I/O | McBSP-B transmit clock | |||
OUTPUTXBAR3 | 6 | O | Output 3 of the output XBAR | |||
UPP-D6 | 15 | I/O | Universal parallel port data line 6 | |||
GPIO15 | 0, 4, 8, 12 | D3 | 7 | I/O | General-purpose input/output 15 | |
EPWM8B | 1 | O | Enhanced PWM8 output B (HRPWM-capable) | |||
SCIRXDB | 2 | I | SCI-B receive data | |||
MFSXB | 3 | I/O | McBSP-B transmit frame synch | |||
OUTPUTXBAR4 | 6 | O | Output 4 of the output XBAR | |||
UPP-D5 | 15 | I/O | Universal parallel port data line 5 | |||
GPIO16 | 0, 4, 8, 12 | E1 | 8 | I/O | General-purpose input/output 16 | |
SPISIMOA | 1 | I/O | SPI-A slave in, master out | |||
CANTXB | 2 | O | CAN-B transmit | |||
OUTPUTXBAR7 | 3 | O | Output 7 of the output XBAR | |||
EPWM9A | 5 | O | Enhanced PWM9 output A | |||
SD1_D1 | 7 | I | Sigma-Delta 1 channel 1 data input | |||
UPP-D4 | 15 | I/O | Universal parallel port data line 4 | |||
GPIO17 | 0, 4, 8, 12 | E2 | 9 | I/O | General-purpose input/output 17 | |
SPISOMIA | 1 | I/O | SPI-A slave out, master in | |||
CANRXB | 2 | I | CAN-B receive | |||
OUTPUTXBAR8 | 3 | O | Output 8 of the output XBAR | |||
EPWM9B | 5 | O | Enhanced PWM9 output B | |||
SD1_C1 | 7 | I | Sigma-Delta 1 channel 1 clock input | |||
UPP-D3 | 15 | I/O | Universal parallel port data line 3 | |||
GPIO18 | 0, 4, 8, 12 | E3 | 10 | I/O | General-purpose input/output 18 | |
SPICLKA | 1 | I/O | SPI-A clock | |||
SCITXDB | 2 | O | SCI-B transmit data | |||
CANRXA | 3 | I | CAN-A receive | |||
EPWM10A | 5 | O | Enhanced PWM10 output A | |||
SD1_D2 | 7 | I | Sigma-Delta 1 channel 2 data input | |||
UPP-D2 | 15 | I/O | Universal parallel port data line 2 | |||
GPIO19 | 0, 4, 8, 12 | E4 | 12 | I/O | General-purpose input/output 19 | |
SPISTEA | 1 | I/O | SPI-A slave transmit enable | |||
SCIRXDB | 2 | I | SCI-B receive data | |||
CANTXA | 3 | O | CAN-A transmit | |||
EPWM10B | 5 | O | Enhanced PWM10 output B | |||
SD1_C2 | 7 | I | Sigma-Delta 1 channel 2 clock input | |||
UPP-D1 | 15 | I/O | Universal parallel port data line 1 | |||
GPIO20 | 0, 4, 8, 12 | F2 | 13 | I/O | General-purpose input/output 20 | |
EQEP1A | 1 | I | Enhanced QEP1 input A | |||
MDXA | 2 | O | McBSP-A transmit serial data | |||
CANTXB | 3 | O | CAN-B transmit | |||
EPWM11A | 5 | O | Enhanced PWM11 output A | |||
SD1_D3 | 7 | I | Sigma-Delta 1 channel 3 data input | |||
UPP-D0 | 15 | I/O | Universal parallel port data line 0 | |||
GPIO21 | 0, 4, 8, 12 | F3 | 14 | I/O | General-purpose input/output 21 | |
EQEP1B | 1 | I | Enhanced QEP1 input B | |||
MDRA | 2 | I | McBSP-A receive serial data | |||
CANRXB | 3 | I | CAN-B receive | |||
EPWM11B | 5 | O | Enhanced PWM11 output B | |||
SD1_C3 | 7 | I | Sigma-Delta 1 channel 3 clock input | |||
UPP-CLK | 15 | I/O | Universal parallel port transmit clock | |||
GPIO22 | 0, 4, 8, 12 | J4 | 22 | I/O | General-purpose input/output 22 | |
EQEP1S | 1 | I/O | Enhanced QEP1 strobe | |||
MCLKXA | 2 | I/O | McBSP-A transmit clock | |||
SCITXDB | 3 | O | SCI-B transmit data | |||
EPWM12A | 5 | O | Enhanced PWM12 output A | |||
SPICLKB | 6 | I/O | SPI-B clock | |||
SD1_D4 | 7 | I | Sigma-Delta 1 channel 4 data input | |||
GPIO23 | 0, 4, 8, 12 | K4 | 23 | I/O | General-purpose input/output 23 | |
EQEP1I | 1 | I/O | Enhanced QEP1 index | |||
MFSXA | 2 | I/O | McBSP-A transmit frame synch | |||
SCIRXDB | 3 | I | SCI-B receive data | |||
EPWM12B | 5 | O | Enhanced PWM12 output B | |||
SPISTEB | 6 | I/O | SPI-B slave transmit enable | |||
SD1_C4 | 7 | I | Sigma-Delta 1 channel 4 clock input | |||
GPIO24 | 0, 4, 8, 12 | K3 | 24 | I/O | General-purpose input/output 24 | |
OUTPUTXBAR1 | 1 | O | Output 1 of the output XBAR | |||
EQEP2A | 2 | I | Enhanced QEP2 input A | |||
MDXB | 3 | O | McBSP-B transmit serial data | |||
SPISIMOB | 6 | I/O | SPI-B slave in, master out | |||
SD2_D1 | 7 | I | Sigma-Delta 2 channel 1 data input | |||
GPIO25 | 0, 4, 8, 12 | K2 | 25 | I/O | General-purpose input/output 25 | |
OUTPUTXBAR2 | 1 | O | Output 2 of the output XBAR | |||
EQEP2B | 2 | I | Enhanced QEP2 input B | |||
MDRB | 3 | I | McBSP-B receive serial data | |||
SPISOMIB | 6 | I/O | SPI-B slave out, master in | |||
SD2_C1 | 7 | I | Sigma-Delta 2 channel 1 clock input | |||
GPIO26 | 0, 4, 8, 12 | K1 | 27 | I/O | General-purpose input/output 26 | |
OUTPUTXBAR3 | 1 | O | Output 3 of the output XBAR | |||
EQEP2I | 2 | I/O | Enhanced QEP2 index | |||
MCLKXB | 3 | I/O | McBSP-B transmit clock | |||
OUTPUTXBAR3 | 5 | O | Output 3 of the output XBAR | |||
SPICLKB | 6 | I/O | SPI-B clock | |||
SD2_D2 | 7 | I | Sigma-Delta 2 channel 2 data input | |||
GPIO27 | 0, 4, 8, 12 | L1 | 28 | I/O | General-purpose input/output 27 | |
OUTPUTXBAR4 | 1 | O | Output 4 of the output XBAR | |||
EQEP2S | 2 | I/O | Enhanced QEP2 strobe | |||
MFSXB | 3 | I/O | McBSP-B transmit frame synch | |||
OUTPUTXBAR4 | 5 | O | Output 4 of the output XBAR | |||
SPISTEB | 6 | I/O | SPI-B slave transmit enable | |||
SD2_C2 | 7 | I | Sigma-Delta 2 channel 2 clock input | |||
GPIO28 | 0, 4, 8, 12 | V11 | 64 | I/O | General-purpose input/output 28 | |
SCIRXDA | 1 | I | SCI-A receive data | |||
EM1CS4 | 2 | O | External memory interface 1 chip select 4 | |||
OUTPUTXBAR5 | 5 | O | Output 5 of the output XBAR | |||
EQEP3A | 6 | I | Enhanced QEP3 input A | |||
SD2_D3 | 7 | I | Sigma-Delta 2 channel 3 data input | |||
GPIO29 | 0, 4, 8, 12 | W11 | 65 | I/O | General-purpose input/output 29 | |
SCITXDA | 1 | O | SCI-A transmit data | |||
EM1SDCKE | 2 | O | External memory interface 1 SDRAM clock enable | |||
OUTPUTXBAR6 | 5 | O | Output 6 of the output XBAR | |||
EQEP3B | 6 | I | Enhanced QEP3 input B | |||
SD2_C3 | 7 | I | Sigma-Delta 2 channel 3 clock input | |||
GPIO30 | 0, 4, 8, 12 | T11 | 63 | I/O | General-purpose input/output 30 | |
CANRXA | 1 | I | CAN-A receive | |||
EM1CLK | 2 | O | External memory interface 1 clock | |||
OUTPUTXBAR7 | 5 | O | Output 7 of the output XBAR | |||
EQEP3S | 6 | I/O | Enhanced QEP3 strobe | |||
SD2_D4 | 7 | I | Sigma-Delta 2 channel 4 data input | |||
GPIO31 | 0, 4, 8, 12 | U11 | 66 | I/O | General-purpose input/output 31 | |
CANTXA | 1 | O | CAN-A transmit | |||
EM1WE | 2 | O | External memory interface 1 write enable | |||
OUTPUTXBAR8 | 5 | O | Output 8 of the output XBAR | |||
EQEP3I | 6 | I/O | Enhanced QEP3 index | |||
SD2_C4 | 7 | I | Sigma-Delta 2 channel 4 clock input | |||
GPIO32 | 0, 4, 8, 12 | U13 | 67 | I/O | General-purpose input/output 32 | |
SDAA | 1 | I/OD | I2C-A data open-drain bidirectional port | |||
EM1CS0 | 2 | O | External memory interface 1 chip select 0 | |||
GPIO33 | 0, 4, 8, 12 | T13 | 69 | I/O | General-purpose input/output 33 | |
SCLA | 1 | I/OD | I2C-A clock open-drain bidirectional port | |||
EM1RNW | 2 | O | External memory interface 1 read not write | |||
GPIO34 | 0, 4, 8, 12 | U14 | 70 | I/O | General-purpose input/output 34 | |
OUTPUTXBAR1 | 1 | O | Output 1 of the output XBAR | |||
EM1CS2 | 2 | O | External memory interface 1 chip select 2 | |||
SDAB | 6 | I/OD | I2C-B data open-drain bidirectional port | |||
GPIO35 | 0, 4, 8, 12 | T14 | 71 | I/O | General-purpose input/output 35 | |
SCIRXDA | 1 | I | SCI-A receive data | |||
EM1CS3 | 2 | O | External memory interface 1 chip select 3 | |||
SCLB | 6 | I/OD | I2C-B clock open-drain bidirectional port | |||
GPIO36 | 0, 4, 8, 12 | V16 | 83 | I/O | General-purpose input/output 36 | |
SCITXDA | 1 | O | SCI-A transmit data | |||
EM1WAIT | 2 | I | External memory interface 1 Asynchronous SRAM WAIT | |||
CANRXA | 6 | I | CAN-A receive | |||
GPIO37 | 0, 4, 8, 12 | U16 | 84 | I/O | General-purpose input/output 37 | |
OUTPUTXBAR2 | 1 | O | Output 2 of the output XBAR | |||
EM1OE | 2 | O | External memory interface 1 output enable | |||
CANTXA | 6 | O | CAN-A transmit | |||
GPIO38 | 0, 4, 8, 12 | T16 | 85 | I/O | General-purpose input/output 38 | |
EM1A0 | 2 | O | External memory interface 1 address line 0 | |||
SCITXDC | 5 | O | SCI-C transmit data | |||
CANTXB | 6 | O | CAN-B transmit | |||
GPIO39 | 0, 4, 8, 12 | W17 | 86 | I/O | General-purpose input/output 39 | |
EM1A1 | 2 | O | External memory interface 1 address line 1 | |||
SCIRXDC | 5 | I | SCI-C receive data | |||
CANRXB | 6 | I | CAN-B receive | |||
GPIO40 | 0, 4, 8, 12 | V17 | 87 | I/O | General-purpose input/output 40 | |
EM1A2 | 2 | O | External memory interface 1 address line 2 | |||
SDAB | 6 | I/OD | I2C-B data open-drain bidirectional port | |||
GPIO41 | 0, 4, 8, 12 | U17 | 89 | I/O | General-purpose input/output 41. For applications using the Hibernate low-power mode, this pin serves as the GPIOHIBWAKE signal. For details, see the Low Power Modes section of the System Control chapter in the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual. | |
EM1A3 | 2 | O | External memory interface 1 address line 3 | |||
SCLB | 6 | I/OD | I2C-B clock open-drain bidirectional port | |||
GPIO42 | 0, 4, 8, 12 | D19 | 130 | I/O | General-purpose input/output 42 | |
SDAA | 6 | I/OD | I2C-A data open-drain bidirectional port | |||
SCITXDA | 15 | O | SCI-A transmit data | |||
USB0DM | Analog | I/O | USB PHY differential data | |||
GPIO43 | 0, 4, 8, 12 | C19 | 131 | I/O | General-purpose input/output 43 | |
SCLA | 6 | I/OD | I2C-A clock open-drain bidirectional port | |||
SCIRXDA | 15 | I | SCI-A receive data | |||
USB0DP | Analog | I/O | USB PHY differential data | |||
GPIO44 | 0, 4, 8, 12 | K18 | 113 | I/O | General-purpose input/output 44 | |
EM1A4 | 2 | O | External memory interface 1 address line 4 | |||
GPIO45 | 0, 4, 8, 12 | K19 | 115 | I/O | General-purpose input/output 45 | |
EM1A5 | 2 | O | External memory interface 1 address line 5 | |||
GPIO46 | 0, 4, 8, 12 | E19 | 128 | I/O | General-purpose input/output 46 | |
EM1A6 | 2 | O | External memory interface 1 address line 6 | |||
SCIRXDD | 6 | I | SCI-D receive data | |||
GPIO47 | 0, 4, 8, 12 | E18 | 129 | I/O | General-purpose input/output 47 | |
EM1A7 | 2 | O | External memory interface 1 address line 7 | |||
SCITXDD | 6 | O | SCI-D transmit data | |||
GPIO48 | 0, 4, 8, 12 | R16 | 90 | I/O | General-purpose input/output 48 | |
OUTPUTXBAR3 | 1 | O | Output 3 of the output XBAR | |||
EM1A8 | 2 | O | External memory interface 1 address line 8 | |||
SCITXDA | 6 | O | SCI-A transmit data | |||
SD1_D1 | 7 | I | Sigma-Delta 1 channel 1 data input | |||
GPIO49 | 0, 4, 8, 12 | R17 | 93 | I/O | General-purpose input/output 49 | |
OUTPUTXBAR4 | 1 | O | Output 4 of the output XBAR | |||
EM1A9 | 2 | O | External memory interface 1 address line 9 | |||
SCIRXDA | 6 | I | SCI-A receive data | |||
SD1_C1 | 7 | I | Sigma-Delta 1 channel 1 clock input | |||
GPIO50 | 0, 4, 8, 12 | R18 | 94 | I/O | General-purpose input/output 50 | |
EQEP1A | 1 | I | Enhanced QEP1 input A | |||
EM1A10 | 2 | O | External memory interface 1 address line 10 | |||
SPISIMOC | 6 | I/O | SPI-C slave in, master out | |||
SD1_D2 | 7 | I | Sigma-Delta 1 channel 2 data input | |||
GPIO51 | 0, 4, 8, 12 | R19 | 95 | I/O | General-purpose input/output 51 | |
EQEP1B | 1 | I | Enhanced QEP1 input B | |||
EM1A11 | 2 | O | External memory interface 1 address line 11 | |||
SPISOMIC | 6 | I/O | SPI-C slave out, master in | |||
SD1_C2 | 7 | I | Sigma-Delta 1 channel 2 clock input | |||
GPIO52 | 0, 4, 8, 12 | P16 | 96 | I/O | General-purpose input/output 52 | |
EQEP1S | 1 | I/O | Enhanced QEP1 strobe | |||
EM1A12 | 2 | O | External memory interface 1 address line 12 | |||
SPICLKC | 6 | I/O | SPI-C clock | |||
SD1_D3 | 7 | I | Sigma-Delta 1 channel 3 data input | |||
GPIO53 | 0, 4, 8, 12 | P17 | 97 | I/O | General-purpose input/output 53 | |
EQEP1I | 1 | I/O | Enhanced QEP1 index | |||
EM1D31 | 2 | I/O | External memory interface 1 data line 31 | |||
EM2D15 | 3 | I/O | External memory interface 2 data line 15 | |||
SPISTEC | 6 | I/O | SPI-C slave transmit enable | |||
SD1_C3 | 7 | I | Sigma-Delta 1 channel 3 clock input | |||
GPIO54 | 0, 4, 8, 12 | P18 | 98 | I/O | General-purpose input/output 54 | |
SPISIMOA | 1 | I/O | SPI-A slave in, master out | |||
EM1D30 | 2 | I/O | External memory interface 1 data line 30 | |||
EM2D14 | 3 | I/O | External memory interface 2 data line 14 | |||
EQEP2A | 5 | I | Enhanced QEP2 input A | |||
SCITXDB | 6 | O | SCI-B transmit data | |||
SD1_D4 | 7 | I | Sigma-Delta 1 channel 4 data input | |||
GPIO55 | 0, 4, 8, 12 | P19 | 100 | I/O | General-purpose input/output 55 | |
SPISOMIA | 1 | I/O | SPI-A slave out, master in | |||
EM1D29 | 2 | I/O | External memory interface 1 data line 29 | |||
EM2D13 | 3 | I/O | External memory interface 2 data line 13 | |||
EQEP2B | 5 | I | Enhanced QEP2 input B | |||
SCIRXDB | 6 | I | SCI-B receive data | |||
SD1_C4 | 7 | I | Sigma-Delta 1 channel 4 clock input | |||
GPIO56 | 0, 4, 8, 12 | N16 | 101 | I/O | General-purpose input/output 56 | |
SPICLKA | 1 | I/O | SPI-A clock | |||
EM1D28 | 2 | I/O | External memory interface 1 data line 28 | |||
EM2D12 | 3 | I/O | External memory interface 2 data line 12 | |||
EQEP2S | 5 | I/O | Enhanced QEP2 strobe | |||
SCITXDC | 6 | O | SCI-C transmit data | |||
SD2_D1 | 7 | I | Sigma-Delta 2 channel 1 data input | |||
GPIO57 | 0, 4, 8, 12 | N18 | 102 | I/O | General-purpose input/output 57 | |
SPISTEA | 1 | I/O | SPI-A slave transmit enable | |||
EM1D27 | 2 | I/O | External memory interface 1 data line 27 | |||
EM2D11 | 3 | I/O | External memory interface 2 data line 11 | |||
EQEP2I | 5 | I/O | Enhanced QEP2 index | |||
SCIRXDC | 6 | I | SCI-C receive data | |||
SD2_C1 | 7 | I | Sigma-Delta 2 channel 1 clock input | |||
GPIO58 | 0, 4, 8, 12 | N17 | 103 | I/O | General-purpose input/output 58 | |
MCLKRA | 1 | I/O | McBSP-A receive clock | |||
EM1D26 | 2 | I/O | External memory interface 1 data line 26 | |||
EM2D10 | 3 | I/O | External memory interface 2 data line 10 | |||
OUTPUTXBAR1 | 5 | O | Output 1 of the output XBAR | |||
SPICLKB | 6 | I/O | SPI-B clock | |||
SD2_D2 | 7 | I | Sigma-Delta 2 channel 2 data input | |||
SPISIMOA | 15 | I/O | SPI-A slave in, master out(2) | |||
GPIO59 | 0, 4, 8, 12 | M16 | 104 | I/O | General-purpose input/output 59(3) | |
MFSRA | 1 | I/O | McBSP-A receive frame synch | |||
EM1D25 | 2 | I/O | External memory interface 1 data line 25 | |||
EM2D9 | 3 | I/O | External memory interface 2 data line 9 | |||
OUTPUTXBAR2 | 5 | O | Output 2 of the output XBAR | |||
SPISTEB | 6 | I/O | SPI-B slave transmit enable | |||
SD2_C2 | 7 | I | Sigma-Delta 2 channel 2 clock input | |||
SPISOMIA | 15 | I/O | SPI-A slave out, master in(2) | |||
GPIO60 | 0, 4, 8, 12 | M17 | 105 | I/O | General-purpose input/output 60 | |
MCLKRB | 1 | I/O | McBSP-B receive clock | |||
EM1D24 | 2 | I/O | External memory interface 1 data line 24 | |||
EM2D8 | 3 | I/O | External memory interface 2 data line 8 | |||
OUTPUTXBAR3 | 5 | O | Output 3 of the output XBAR | |||
SPISIMOB | 6 | I/O | SPI-B slave in, master out | |||
SD2_D3 | 7 | I | Sigma-Delta 2 channel 3 data input | |||
SPICLKA | 15 | I/O | SPI-A clock(2) | |||
GPIO61 | 0, 4, 8, 12 | L16 | 107 | I/O | General-purpose input/output 61(3) | |
MFSRB | 1 | I/O | McBSP-B receive frame synch | |||
EM1D23 | 2 | I/O | External memory interface 1 data line 23 | |||
EM2D7 | 3 | I/O | External memory interface 2 data line 7 | |||
OUTPUTXBAR4 | 5 | O | Output 4 of the output XBAR | |||
SPISOMIB | 6 | I/O | SPI-B slave out, master in | |||
SD2_C3 | 7 | I | Sigma-Delta 2 channel 3 clock input | |||
SPISTEA | 15 | I/O | SPI-A slave transmit enable(2) | |||
GPIO62 | 0, 4, 8, 12 | J17 | 108 | I/O | General-purpose input/output 62 | |
SCIRXDC | 1 | I | SCI-C receive data | |||
EM1D22 | 2 | I/O | External memory interface 1 data line 22 | |||
EM2D6 | 3 | I/O | External memory interface 2 data line 6 | |||
EQEP3A | 5 | I | Enhanced QEP3 input A | |||
CANRXA | 6 | I | CAN-A receive | |||
SD2_D4 | 7 | I | Sigma-Delta 2 channel 4 data input | |||
GPIO63 | 0, 4, 8, 12 | J16 | 109 | I/O | General-purpose input/output 63 | |
SCITXDC | 1 | O | SCI-C transmit data | |||
EM1D21 | 2 | I/O | External memory interface 1 data line 21 | |||
EM2D5 | 3 | I/O | External memory interface 2 data line 5 | |||
EQEP3B | 5 | I | Enhanced QEP3 input B | |||
CANTXA | 6 | O | CAN-A transmit | |||
SD2_C4 | 7 | I | Sigma-Delta 2 channel 4 clock input | |||
SPISIMOB | 15 | I/O | SPI-B slave in, master out(2) | |||
GPIO64 | 0, 4, 8, 12 | L17 | 110 | I/O | General-purpose input/output 64(3) | |
EM1D20 | 2 | I/O | External memory interface 1 data line 20 | |||
EM2D4 | 3 | I/O | External memory interface 2 data line 4 | |||
EQEP3S | 5 | I/O | Enhanced QEP3 strobe | |||
SCIRXDA | 6 | I | SCI-A receive data | |||
SPISOMIB | 15 | I/O | SPI-B slave out, master in(2) | |||
GPIO65 | 0, 4, 8, 12 | K16 | 111 | I/O | General-purpose input/output 65 | |
EM1D19 | 2 | I/O | External memory interface 1 data line 19 | |||
EM2D3 | 3 | I/O | External memory interface 2 data line 3 | |||
EQEP3I | 5 | I/O | Enhanced QEP3 index | |||
SCITXDA | 6 | O | SCI-A transmit data | |||
SPICLKB | 15 | I/O | SPI-B clock(2) | |||
GPIO66 | 0, 4, 8, 12 | K17 | 112 | I/O | General-purpose input/output 66(3) | |
EM1D18 | 2 | I/O | External memory interface 1 data line 18 | |||
EM2D2 | 3 | I/O | External memory interface 2 data line 2 | |||
SDAB | 6 | I/OD | I2C-B data open-drain bidirectional port | |||
SPISTEB | 15 | I/O | SPI-B slave transmit enable(2) | |||
GPIO67 | 0, 4, 8, 12 | B19 | 132 | I/O | General-purpose input/output 67 | |
EM1D17 | 2 | I/O | External memory interface 1 data line 17 | |||
EM2D1 | 3 | I/O | External memory interface 2 data line 1 | |||
GPIO68 | 0, 4, 8, 12 | C18 | 133 | I/O | General-purpose input/output 68 | |
EM1D16 | 2 | I/O | External memory interface 1 data line 16 | |||
EM2D0 | 3 | I/O | External memory interface 2 data line 0 | |||
GPIO69 | 0, 4, 8, 12 | B18 | 134 | I/O | General-purpose input/output 69 | |
EM1D15 | 2 | I/O | External memory interface 1 data line 15 | |||
SCLB | 6 | I/OD | I2C-B clock open-drain bidirectional port | |||
SPISIMOC | 15 | I/O | SPI-C slave in, master out(2) | |||
GPIO70 | 0, 4, 8, 12 | A17 | 135 | I/O | General-purpose input/output 70(3) | |
EM1D14 | 2 | I/O | External memory interface 1 data line 14 | |||
CANRXA | 5 | I | CAN-A receive | |||
SCITXDB | 6 | O | SCI-B transmit data | |||
SPISOMIC | 15 | I/O | SPI-C slave out, master in(2) | |||
GPIO71 | 0, 4, 8, 12 | B17 | 136 | I/O | General-purpose input/output 71 | |
EM1D13 | 2 | I/O | External memory interface 1 data line 13 | |||
CANTXA | 5 | O | CAN-A transmit | |||
SCIRXDB | 6 | I | SCI-B receive data | |||
SPICLKC | 15 | I/O | SPI-C clock(2) | |||
GPIO72 | 0, 4, 8, 12 | B16 | 139 | I/O | General-purpose input/output 72.(3) This is the factory default boot mode select pin 1. | |
EM1D12 | 2 | I/O | External memory interface 1 data line 12 | |||
CANTXB | 5 | O | CAN-B transmit | |||
SCITXDC | 6 | O | SCI-C transmit data | |||
SPISTEC | 15 | I/O | SPI-C slave transmit enable(2) | |||
GPIO73 | 0, 4, 8, 12 | A16 | 140 | I/O | General-purpose input/output 73 | |
EM1D11 | 2 | I/O | External memory interface 1 data line 11 | |||
XCLKOUT | 3 | O/Z | External clock output. This pin outputs a divided-down version of a chosen clock signal from within the device. The clock signal is chosen using the CLKSRCCTL3.XCLKOUTSEL bit field while the divide ratio is chosen using the XCLKOUTDIVSEL.XCLKOUTDIV bit field. | |||
CANRXB | 5 | I | CAN-B receive | |||
SCIRXDC | 6 | I | SCI-C receive | |||
GPIO74 | 0, 4, 8, 12 | C17 | 141 | I/O | General-purpose input/output 74 | |
EM1D10 | 2 | I/O | External memory interface 1 data line 10 | |||
GPIO75 | 0, 4, 8, 12 | D16 | 142 | I/O | General-purpose input/output 75 | |
EM1D9 | 2 | I/O | External memory interface 1 data line 9 | |||
GPIO76 | 0, 4, 8, 12 | C16 | 143 | I/O | General-purpose input/output 76 | |
EM1D8 | 2 | I/O | External memory interface 1 data line 8 | |||
SCITXDD | 6 | O | SCI-D transmit data | |||
GPIO77 | 0, 4, 8, 12 | A15 | 144 | I/O | General-purpose input/output 77 | |
EM1D7 | 2 | I/O | External memory interface 1 data line 7 | |||
SCIRXDD | 6 | I | SCI-D receive data | |||
GPIO78 | 0, 4, 8, 12 | B15 | 145 | I/O | General-purpose input/output 78 | |
EM1D6 | 2 | I/O | External memory interface 1 data line 6 | |||
EQEP2A | 6 | I | Enhanced QEP2 input A | |||
GPIO79 | 0, 4, 8, 12 | C15 | 146 | I/O | General-purpose input/output 79 | |
EM1D5 | 2 | I/O | External memory interface 1 data line 5 | |||
EQEP2B | 6 | I | Enhanced QEP2 input B | |||
GPIO80 | 0, 4, 8, 12 | D15 | 148 | I/O | General-purpose input/output 80 | |
EM1D4 | 2 | I/O | External memory interface 1 data line 4 | |||
EQEP2S | 6 | I/O | Enhanced QEP2 strobe | |||
GPIO81 | 0, 4, 8, 12 | A14 | 149 | I/O | General-purpose input/output 81 | |
EM1D3 | 2 | I/O | External memory interface 1 data line 3 | |||
EQEP2I | 6 | I/O | Enhanced QEP2 index | |||
GPIO82 | 0, 4, 8, 12 | B14 | 150 | I/O | General-purpose input/output 82 | |
EM1D2 | 2 | I/O | External memory interface 1 data line 2 | |||
GPIO83 | 0, 4, 8, 12 | C14 | 151 | I/O | General-purpose input/output 83 | |
EM1D1 | 2 | I/O | External memory interface 1 data line 1 | |||
GPIO84 | 0, 4, 8, 12 | A11 | 154 | I/O | General-purpose input/output 84. This is the factory default boot mode select pin 0. | |
SCITXDA | 5 | O | SCI-A transmit data | |||
MDXB | 6 | O | McBSP-B transmit serial data | |||
MDXA | 15 | O | McBSP-A transmit serial data | |||
GPIO85 | 0, 4, 8, 12 | B11 | 155 | I/O | General-purpose input/output 85 | |
EM1D0 | 2 | I/O | External memory interface 1 data line 0 | |||
SCIRXDA | 5 | I | SCI-A receive data | |||
MDRB | 6 | I | McBSP-B receive serial data | |||
MDRA | 15 | I | McBSP-A receive serial data | |||
GPIO86 | 0, 4, 8, 12 | C11 | 156 | I/O | General-purpose input/output 86 | |
EM1A13 | 2 | O | External memory interface 1 address line 13 | |||
EM1CAS | 3 | O | External memory interface 1 column address strobe | |||
SCITXDB | 5 | O | SCI-B transmit data | |||
MCLKXB | 6 | I/O | McBSP-B transmit clock | |||
MCLKXA | 15 | I/O | McBSP-A transmit clock | |||
GPIO87 | 0, 4, 8, 12 | D11 | 157 | I/O | General-purpose input/output 87 | |
EM1A14 | 2 | O | External memory interface 1 address line 14 | |||
EM1RAS | 3 | O | External memory interface 1 row address strobe | |||
SCIRXDB | 5 | I | SCI-B receive data | |||
MFSXB | 6 | I/O | McBSP-B transmit frame synch | |||
MFSXA | 15 | I/O | McBSP-A transmit frame synch | |||
GPIO88 | 0, 4, 8, 12 | C6 | 170 | I/O | General-purpose input/output 88 | |
EM1A15 | 2 | O | External memory interface 1 address line 15 | |||
EM1DQM0 | 3 | O | External memory interface 1 Input/output mask for byte 0 | |||
GPIO89 | 0, 4, 8, 12 | D6 | 171 | I/O | General-purpose input/output 89 | |
EM1A16 | 2 | O | External memory interface 1 address line 16 | |||
EM1DQM1 | 3 | O | External memory interface 1 Input/output mask for byte 1 | |||
SCITXDC | 6 | O | SCI-C transmit data | |||
GPIO90 | 0, 4, 8, 12 | A5 | 172 | I/O | General-purpose input/output 90 | |
EM1A17 | 2 | O | External memory interface 1 address line 17 | |||
EM1DQM2 | 3 | O | External memory interface 1 Input/output mask for byte 2 | |||
SCIRXDC | 6 | I | SCI-C receive data | |||
GPIO91 | 0, 4, 8, 12 | B5 | 173 | I/O | General-purpose input/output 91 | |
EM1A18 | 2 | O | External memory interface 1 address line 18 | |||
EM1DQM3 | 3 | O | External memory interface 1 Input/output mask for byte 3 | |||
SDAA | 6 | I/OD | I2C-A data open-drain bidirectional port | |||
GPIO92 | 0, 4, 8, 12 | A4 | 174 | I/O | General-purpose input/output 92 | |
EM1A19 | 2 | O | External memory interface 1 address line 19 | |||
EM1BA1 | 3 | O | External memory interface 1 bank address 1 | |||
SCLA | 6 | I/OD | I2C-A clock open-drain bidirectional port | |||
GPIO93 | 0, 4, 8, 12 | B4 | 175 | I/O | General-purpose input/output 93 | |
EM1BA0 | 3 | O | External memory interface 1 bank address 0 | |||
SCITXDD | 6 | O | SCI-D transmit data | |||
GPIO94 | 0, 4, 8, 12 | A3 | 176 | I/O | General-purpose input/output 94 | |
SCIRXDD | 6 | I | SCI-D receive data | |||
GPIO95 | 0, 4, 8, 12 | B3 | — | I/O | General-purpose input/output 95 | |
GPIO96 | 0, 4, 8, 12 | C3 | — | I/O | General-purpose input/output 96 | |
EM2DQM1 | 3 | O | External memory interface 2 Input/output mask for byte 1 | |||
EQEP1A | 5 | I | Enhanced QEP1 input A | |||
GPIO97 | 0, 4, 8, 12 | A2 | — | I/O | General-purpose input/output 97 | |
EM2DQM0 | 3 | O | External memory interface 2 Input/output mask for byte 0 | |||
EQEP1B | 5 | I | Enhanced QEP1 input B | |||
GPIO98 | 0, 4, 8, 12 | F1 | — | I/O | General-purpose input/output 98 | |
EM2A0 | 3 | O | External memory interface 2 address line 0 | |||
EQEP1S | 5 | I/O | Enhanced QEP1 strobe | |||
GPIO99 | 0, 4, 8, 12 | G1 | 17 | I/O | General-purpose input/output 99 | |
EM2A1 | 3 | O | External memory interface 2 address line 1 | |||
EQEP1I | 5 | I/O | Enhanced QEP1 index | |||
GPIO100 | 0, 4, 8, 12 | H1 | — | I/O | General-purpose input/output 100 | |
EM2A2 | 3 | O | External memory interface 2 address line 2 | |||
EQEP2A | 5 | I | Enhanced QEP2 input A | |||
SPISIMOC | 6 | I/O | SPI-C slave in, master out | |||
GPIO101 | 0, 4, 8, 12 | H2 | — | I/O | General-purpose input/output 101 | |
EM2A3 | 3 | O | External memory interface 2 address line 3 | |||
EQEP2B | 5 | I | Enhanced QEP2 input B | |||
SPISOMIC | 6 | I/O | SPI-C slave out, master in | |||
GPIO102 | 0, 4, 8, 12 | H3 | — | I/O | General-purpose input/output 102 | |
EM2A4 | 3 | O | External memory interface 2 address line 4 | |||
EQEP2S | 5 | I/O | Enhanced QEP2 strobe | |||
SPICLKC | 6 | I/O | SPI-C clock | |||
GPIO103 | 0, 4, 8, 12 | J1 | — | I/O | General-purpose input/output 103 | |
EM2A5 | 3 | O | External memory interface 2 address line 5 | |||
EQEP2I | 5 | I/O | Enhanced QEP2 index | |||
SPISTEC | 6 | I/O | SPI-C slave transmit enable | |||
GPIO104 | 0, 4, 8, 12 | J2 | — | I/O | General-purpose input/output 104 | |
SDAA | 1 | I/OD | I2C-A data open-drain bidirectional port | |||
EM2A6 | 3 | O | External memory interface 2 address line 6 | |||
EQEP3A | 5 | I | Enhanced QEP3 input A | |||
SCITXDD | 6 | O | SCI-D transmit data | |||
GPIO105 | 0, 4, 8, 12 | J3 | — | I/O | General-purpose input/output 105 | |
SCLA | 1 | I/OD | I2C-A clock open-drain bidirectional port | |||
EM2A7 | 3 | O | External memory interface 2 address line 7 | |||
EQEP3B | 5 | I | Enhanced QEP3 input B | |||
SCIRXDD | 6 | I | SCI-D receive data | |||
GPIO106 | 0, 4, 8, 12 | L2 | — | I/O | General-purpose input/output 106 | |
EM2A8 | 3 | O | External memory interface 2 address line 8 | |||
EQEP3S | 5 | I/O | Enhanced QEP3 strobe | |||
SCITXDC | 6 | O | SCI-C transmit data | |||
GPIO107 | 0, 4, 8, 12 | L3 | — | I/O | General-purpose input/output 107 | |
EM2A9 | 3 | O | External memory interface 2 address line 9 | |||
EQEP3I | 5 | I/O | Enhanced QEP3 index | |||
SCIRXDC | 6 | I | SCI-C receive data | |||
GPIO108 | 0, 4, 8, 12 | L4 | — | I/O | General-purpose input/output 108 | |
EM2A10 | 3 | O | External memory interface 2 address line 10 | |||
GPIO109 | 0, 4, 8, 12 | N2 | — | I/O | General-purpose input/output 109 | |
EM2A11 | 3 | O | External memory interface 2 address line 11 | |||
GPIO110 | 0, 4, 8, 12 | M2 | — | I/O | General-purpose input/output 110 | |
EM2WAIT | 3 | I | External memory interface 2 Asynchronous SRAM WAIT | |||
GPIO111 | 0, 4, 8, 12 | M4 | — | I/O | General-purpose input/output 111 | |
EM2BA0 | 3 | O | External memory interface 2 bank address 0 | |||
GPIO112 | 0, 4, 8, 12 | M3 | — | I/O | General-purpose input/output 112 | |
EM2BA1 | 3 | O | External memory interface 2 bank address 1 | |||
GPIO113 | 0, 4, 8, 12 | N4 | — | I/O | General-purpose input/output 113 | |
EM2CAS | 3 | O | External memory interface 2 column address strobe | |||
GPIO114 | 0, 4, 8, 12 | N3 | — | I/O | General-purpose input/output 114 | |
EM2RAS | 3 | O | External memory interface 2 row address strobe | |||
GPIO115 | 0, 4, 8, 12 | V12 | — | I/O | General-purpose input/output 115 | |
EM2CS0 | 3 | O | External memory interface 2 chip select 0 | |||
GPIO116 | 0, 4, 8, 12 | W10 | — | I/O | General-purpose input/output 116 | |
EM2CS2 | 3 | O | External memory interface 2 chip select 2 | |||
GPIO117 | 0, 4, 8, 12 | U12 | — | I/O | General-purpose input/output 117 | |
EM2SDCKE | 3 | O | External memory interface 2 SDRAM clock enable | |||
GPIO118 | 0, 4, 8, 12 | T12 | — | I/O | General-purpose input/output 118 | |
EM2CLK | 3 | O | External memory interface 2 clock | |||
GPIO119 | 0, 4, 8, 12 | T15 | — | I/O | General-purpose input/output 119 | |
EM2RNW | 3 | O | External memory interface 2 read not write | |||
GPIO120 | 0, 4, 8, 12 | U15 | — | I/O | General-purpose input/output 120 | |
EM2WE | 3 | O | External memory interface 2 write enable | |||
USB0PFLT | 15 | I/O | USB external regulator power fault indicator | |||
GPIO121 | 0, 4, 8, 12 | W16 | — | I/O | General-purpose input/output 121 | |
EM2OE | 3 | O | External memory interface 2 output enable | |||
USB0EPEN | 15 | I/O | USB external regulator enable | |||
GPIO122 | 0, 4, 8, 12 | T8 | — | I/O | General-purpose input/output 122 | |
SPISIMOC | 6 | I/O | SPI-C slave in, master out | |||
SD1_D1 | 7 | I | Sigma-Delta 1 channel 1 data input | |||
GPIO123 | 0, 4, 8, 12 | U8 | — | I/O | General-purpose input/output 123 | |
SPISOMIC | 6 | I/O | SPI-C slave out, master in | |||
SD1_C1 | 7 | I | Sigma-Delta 1 channel 1 clock input | |||
GPIO124 | 0, 4, 8, 12 | V8 | — | I/O | General-purpose input/output 124 | |
SPICLKC | 6 | I/O | SPI-C clock | |||
SD1_D2 | 7 | I | Sigma-Delta 1 channel 2 data input | |||
GPIO125 | 0, 4, 8, 12 | T9 | — | I/O | General-purpose input/output 125 | |
SPISTEC | 6 | I/O | SPI-C slave transmit enable | |||
SD1_C2 | 7 | I | Sigma-Delta 1 channel 2 clock input | |||
GPIO126 | 0, 4, 8, 12 | U9 | — | I/O | General-purpose input/output 126 | |
SD1_D3 | 7 | I | Sigma-Delta 1 channel 3 data input | |||
GPIO127 | 0, 4, 8, 12 | V9 | — | I/O | General-purpose input/output 127 | |
SD1_C3 | 7 | I | Sigma-Delta 1 channel 3 clock input | |||
GPIO128 | 0, 4, 8, 12 | W9 | — | I/O | General-purpose input/output 128 | |
SD1_D4 | 7 | I | Sigma-Delta 1 channel 4 data input | |||
GPIO129 | 0, 4, 8, 12 | T10 | — | I/O | General-purpose input/output 129 | |
SD1_C4 | 7 | I | Sigma-Delta 1 channel 4 clock input | |||
GPIO130 | 0, 4, 8, 12 | U10 | — | I/O | General-purpose input/output 130 | |
SD2_D1 | 7 | I | Sigma-Delta 2 channel 1 data input | |||
GPIO131 | 0, 4, 8, 12 | V10 | — | I/O | General-purpose input/output 131 | |
SD2_C1 | 7 | I | Sigma-Delta 2 channel 1 clock input | |||
GPIO132 | 0, 4, 8, 12 | W18 | — | I/O | General-purpose input/output 132 | |
SD2_D2 | 7 | I | Sigma-Delta 2 channel 2 data input | |||
GPIO133/AUXCLKIN | 0, 4, 8, 12 | G18 | 118 | I/O | General-purpose input/output 133. The AUXCLKIN function of this GPIO pin could be used to provide a single-ended 3.3-V level clock signal to the Auxiliary Phase-Locked Loop (AUXPLL), whose output is used for the USB module. The AUXCLKIN clock may also be used for the CAN module. | |
SD2_C2 | 7 | I | Sigma-Delta 2 channel 2 clock input | |||
GPIO134 | 0, 4, 8, 12 | V18 | — | I/O | General-purpose input/output 134 | |
SD2_D3 | 7 | I | Sigma-Delta 2 channel 3 data input | |||
GPIO135 | 0, 4, 8, 12 | U18 | — | I/O | General-purpose input/output 135 | |
SCITXDA | 6 | O | SCI-A transmit data | |||
SD2_C3 | 7 | I | Sigma-Delta 2 channel 3 clock input | |||
GPIO136 | 0, 4, 8, 12 | T17 | — | I/O | General-purpose input/output 136 | |
SCIRXDA | 6 | I | SCI-A receive data | |||
SD2_D4 | 7 | I | Sigma-Delta 2 channel 4 data input | |||
GPIO137 | 0, 4, 8, 12 | T18 | — | I/O | General-purpose input/output 137 | |
SCITXDB | 6 | O | SCI-B transmit data | |||
SD2_C4 | 7 | I | Sigma-Delta 2 channel 4 clock input | |||
GPIO138 | 0, 4, 8, 12 | T19 | — | I/O | General-purpose input/output 138 | |
SCIRXDB | 6 | I | SCI-B receive data | |||
GPIO139 | 0, 4, 8, 12 | N19 | — | I/O | General-purpose input/output 139 | |
SCIRXDC | 6 | I | SCI-C receive data | |||
GPIO140 | 0, 4, 8, 12 | M19 | — | I/O | General-purpose input/output 140 | |
SCITXDC | 6 | O | SCI-C transmit data | |||
GPIO141 | 0, 4, 8, 12 | M18 | — | I/O | General-purpose input/output 141 | |
SCIRXDD | 6 | I | SCI-D receive data | |||
GPIO142 | 0, 4, 8, 12 | L19 | — | I/O | General-purpose input/output 142 | |
SCITXDD | 6 | O | SCI-D transmit data | |||
GPIO143 | 0, 4, 8, 12 | F18 | — | I/O | General-purpose input/output 143 | |
GPIO144 | 0, 4, 8, 12 | F17 | — | I/O | General-purpose input/output 144 | |
GPIO145 | 0, 4, 8, 12 | E17 | — | I/O | General-purpose input/output 145 | |
EPWM1A | 1 | O | Enhanced PWM1 output A (HRPWM-capable) | |||
GPIO146 | 0, 4, 8, 12 | D18 | — | I/O | General-purpose input/output 146 | |
EPWM1B | 1 | O | Enhanced PWM1 output B (HRPWM-capable) | |||
GPIO147 | 0, 4, 8, 12 | D17 | — | I/O | General-purpose input/output 147 | |
EPWM2A | 1 | O | Enhanced PWM2 output A (HRPWM-capable) | |||
GPIO148 | 0, 4, 8, 12 | D14 | — | I/O | General-purpose input/output 148 | |
EPWM2B | 1 | O | Enhanced PWM2 output B (HRPWM-capable) | |||
GPIO149 | 0, 4, 8, 12 | A13 | — | I/O | General-purpose input/output 149 | |
EPWM3A | 1 | O | Enhanced PWM3 output A (HRPWM-capable) | |||
GPIO150 | 0, 4, 8, 12 | B13 | — | I/O | General-purpose input/output 150 | |
EPWM3B | 1 | O | Enhanced PWM3 output B (HRPWM-capable) | |||
GPIO151 | 0, 4, 8, 12 | C13 | — | I/O | General-purpose input/output 151 | |
EPWM4A | 1 | O | Enhanced PWM4 output A (HRPWM-capable) | |||
GPIO152 | 0, 4, 8, 12 | D13 | — | I/O | General-purpose input/output 152 | |
EPWM4B | 1 | O | Enhanced PWM4 output B (HRPWM-capable) | |||
GPIO153 | 0, 4, 8, 12 | A12 | — | I/O | General-purpose input/output 153 | |
EPWM5A | 1 | O | Enhanced PWM5 output A (HRPWM-capable) | |||
GPIO154 | 0, 4, 8, 12 | B12 | — | I/O | General-purpose input/output 154 | |
EPWM5B | 1 | O | Enhanced PWM5 output B (HRPWM-capable) | |||
GPIO155 | 0, 4, 8, 12 | C12 | — | I/O | General-purpose input/output 155 | |
EPWM6A | 1 | O | Enhanced PWM6 output A (HRPWM-capable) | |||
GPIO156 | 0, 4, 8, 12 | D12 | — | I/O | General-purpose input/output 156 | |
EPWM6B | 1 | O | Enhanced PWM6 output B (HRPWM-capable) | |||
GPIO157 | 0, 4, 8, 12 | B10 | — | I/O | General-purpose input/output 157 | |
EPWM7A | 1 | O | Enhanced PWM7 output A (HRPWM-capable) | |||
GPIO158 | 0, 4, 8, 12 | C10 | — | I/O | General-purpose input/output 158 | |
EPWM7B | 1 | O | Enhanced PWM7 output B (HRPWM-capable) | |||
GPIO159 | 0, 4, 8, 12 | D10 | — | I/O | General-purpose input/output 159 | |
EPWM8A | 1 | O | Enhanced PWM8 output A (HRPWM-capable) | |||
GPIO160 | 0, 4, 8, 12 | B9 | — | I/O | General-purpose input/output 160 | |
EPWM8B | 1 | O | Enhanced PWM8 output B (HRPWM-capable) | |||
GPIO161 | 0, 4, 8, 12 | C9 | — | I/O | General-purpose input/output 161 | |
EPWM9A | 1 | O | Enhanced PWM9 output A | |||
GPIO162 | 0, 4, 8, 12 | D9 | — | I/O | General-purpose input/output 162 | |
EPWM9B | 1 | O | Enhanced PWM9 output B | |||
GPIO163 | 0, 4, 8, 12 | A8 | — | I/O | General-purpose input/output 163 | |
EPWM10A | 1 | O | Enhanced PWM10 output A | |||
GPIO164 | 0, 4, 8, 12 | B8 | — | I/O | General-purpose input/output 164 | |
EPWM10B | 1 | O | Enhanced PWM10 output B | |||
GPIO165 | 0, 4, 8, 12 | C5 | — | I/O | General-purpose input/output 165 | |
EPWM11A | 1 | O | Enhanced PWM11 output A | |||
GPIO166 | 0, 4, 8, 12 | D5 | — | I/O | General-purpose input/output 166 | |
EPWM11B | 1 | O | Enhanced PWM11 output B | |||
GPIO167 | 0, 4, 8, 12 | C4 | — | I/O | General-purpose input/output 167 | |
EPWM12A | 1 | O | Enhanced PWM12 output A | |||
GPIO168 | 0, 4, 8, 12 | D4 | — | I/O | General-purpose input/output 168 | |
EPWM12B | 1 | O | Enhanced PWM12 output B | |||
RESET | ||||||
XRS | F19 | 124 | I/OD | Device Reset (in) and Watchdog Reset (out). The devices have a built-in power-on reset (POR) circuit. During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset or NMI watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. The output buffer of this pin is an open drain with an internal pullup. If this pin is driven by an external device, an open-drain device is recommended. | ||
CLOCKS | ||||||
X1 | G19 | 123 | I | On-chip crystal-oscillator input. To use this oscillator, a quartz crystal must be connected across X1 and X2. If this pin is not used, it must be tied to GND. This pin can also be used to feed a single-ended 3.3-V level clock. In this case, X2 is a No Connect (NC). |
||
X2 | J19 | 121 | O | On-chip crystal-oscillator output. A quartz crystal may be connected across X1 and X2. If X2 is not used, it must be left unconnected. | ||
NO CONNECT | ||||||
NC | H4 | — | No connect. BGA ball is electrically open and not connected to the die. | |||
JTAG | ||||||
TCK | V15 | 81 | I | JTAG test clock with internal pullup (see Section 4.5) | ||
TDI | W13 | 77 | I | JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. | ||
TDO | W15 | 78 | O/Z | JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.(3) | ||
TMS | W14 | 80 | I | JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. | ||
TRST | V14 | 79 | I | JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ or smaller resistor generally offers adequate protection. The value of the resistor is application-specific. TI recommends that each target board be validated for proper operation of the debugger and the application. This pin has an internal 50-ns (nominal) glitch filter. | ||
INTERNAL VOLTAGE REGULATOR CONTROL | ||||||
VREGENZ | J18 | 119 | I | Internal voltage regulator enable with internal pulldown. The internal VREG is not supported and must be disabled. Connect VREGENZ to VDDIO. | ||
ANALOG, DIGITAL, AND I/O POWER | ||||||
VDD | E9 | 16 | 1.2-V digital logic power pins. TI recommends placing a decoupling capacitor near each VDD pin with a minimum total capacitance of approximately 20 uF. The exact value of the decoupling capacitance should be determined by your system voltage regulation solution. | |||
E11 | 21 | |||||
F9 | 61 | |||||
F11 | 76 | |||||
G14 | 117 | |||||
G15 | 126 | |||||
J14 | 137 | |||||
J15 | 153 | |||||
K5 | 158 | |||||
K6 | 169 | |||||
P10 | — | |||||
P13 | — | |||||
R10 | — | |||||
R13 | — | |||||
VDD3VFL | R11 | 72 | 3.3-V Flash power pin. Place a minimum 0.1-µF decoupling capacitor on each pin. | |||
R12 | — | |||||
VDDA | P6 | 36 | 3.3-V analog power pins. Place a minimum 2.2-µF decoupling capacitor to VSSA on each pin. | |||
R6 | 54 | |||||
VDDIO | A9 | 3 | 3.3-V digital I/O power pins. Place a minimum 0.1-µF decoupling capacitor on each pin. The exact value of the decoupling capacitance should be determined by your system voltage regulation solution. | |||
A18 | 11 | |||||
B1 | 15 | |||||
E7 | 20 | |||||
E10 | 26 | |||||
E13 | 62 | |||||
E16 | 68 | |||||
F4 | 75 | |||||
F7 | 82 | |||||
F10 | 88 | |||||
F13 | 91 | |||||
F16 | 99 | |||||
G4 | 106 | |||||
G5 | 114 | |||||
G6 | 116 | |||||
H5 | 127 | |||||
H6 | 138 | |||||
L14 | 147 | |||||
L15 | 152 | |||||
M1 | 159 | |||||
M5 | 168 | |||||
M6 | — | |||||
N14 | — | |||||
N15 | — | |||||
P9 | — | |||||
R9 | — | |||||
V19 | — | |||||
W8 | — | |||||
VDDOSC | H16 | 120 | Power pins for the 3.3-V on-chip crystal oscillator (X1 and X2) and the two zero-pin internal oscillators (INTOSC). Place a 0.1-μF (minimum) decoupling capacitor on each pin. | |||
H17 | 125 | |||||
VSS | A1 | PWR PAD |
Device ground. For Quad Flatpacks (QFPs), the PowerPAD on the bottom of the package must be soldered to the ground plane of the PCB. | |||
A10 | ||||||
A19 | ||||||
E5 | ||||||
E6 | ||||||
E8 | ||||||
E12 | ||||||
E14 | ||||||
E15 | ||||||
F5 | ||||||
F6 | ||||||
F8 | ||||||
F12 | ||||||
F14 | ||||||
F15 | ||||||
G16 | ||||||
G17 | ||||||
H8 | ||||||
H9 | ||||||
H10 | ||||||
H11 | ||||||
H12 | ||||||
H14 | ||||||
H15 | ||||||
J5 | ||||||
J6 | ||||||
J8 | ||||||
J9 | ||||||
J10 | ||||||
J11 | ||||||
J12 | ||||||
K8 | ||||||
K9 | ||||||
K10 | ||||||
K11 | ||||||
K12 | ||||||
K14 | ||||||
K15 | ||||||
L5 | ||||||
L6 | ||||||
L8 | ||||||
L9 | ||||||
VSS | L10 | PWR PAD |
Device ground. For Quad Flatpacks (QFPs), the PowerPAD on the bottom of the package must be soldered to the ground plane of the PCB. | |||
L11 | ||||||
L12 | ||||||
L18 | ||||||
M8 | ||||||
M9 | ||||||
M10 | ||||||
M11 | ||||||
M12 | ||||||
M14 | ||||||
M15 | ||||||
N1 | ||||||
N5 | ||||||
N6 | ||||||
P7 | ||||||
P8 | ||||||
P11 | ||||||
P12 | ||||||
P14 | ||||||
P15 | ||||||
R7 | ||||||
R8 | ||||||
R14 | ||||||
R15 | ||||||
W7 | ||||||
W19 | ||||||
VSSOSC | H18 | 122 | Crystal oscillator (X1 and X2) ground pin. When using an external crystal, do not connect this pin to the board ground. Instead, connect it to the ground reference of the external crystal oscillator circuit. If an external crystal is not used, this pin may be connected to the board ground. |
|||
H19 | — | |||||
VSSA | P1 | 34 | Analog ground. On the PZP package, pin 17 is double-bonded to VSSA and VREFLOA. This pin must be connect to VSSA. |
|||
P5 | 52 | |||||
R5 | — | |||||
V7 | — | |||||
W1 | — | |||||
SPECIAL FUNCTIONS | ||||||
ERRORSTS | U19 | 92 | O | Error status output. This pin has an internal pulldown. | ||
TEST PINS | ||||||
FLT1 | W12 | 73 | I/O | Flash test pin 1. Reserved for TI. Must be left unconnected. | ||
FLT2 | V13 | 74 | I/O | Flash test pin 2. Reserved for TI. Must be left unconnected. |
Some pins on the device have internal pullups or pulldowns. Table 3-2 lists the pull direction and when it is active. The pullups on GPIO pins are disabled by default and can be enabled through software. In order to avoid any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in a particular package. Other pins noted in Table 3-2 with pullups and pulldowns are always on and cannot be disabled.
PIN | RESET (XRS = 0) |
DEVICE BOOT | APPLICATION SOFTWARE |
---|---|---|---|
GPIOx | Pullup disabled | Pullup disabled(1) | Pullup enable is application-defined |
TRST | Pulldown active | ||
TCK | Pullup active | ||
TMS | Pullup active | ||
TDI | Pullup active | ||
XRS | Pullup active | ||
VREGENZ | Pulldown active | ||
ERRORSTS | Pulldown active | ||
Other pins | No pullup or pulldown present |
Table 3-3 shows the GPIO muxed pins. The default for each pin is the GPIO function, secondary functions can be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be configured prior to the GPyMUXn to avoid transient pulses on GPIO's from alternate mux selections. Columns not shown and blank cells are reserved GPIO Mux settings.
GPIO Mux Selection | ||||||||
---|---|---|---|---|---|---|---|---|
GPIO Index | 0, 4, 8, 12 | 1 | 2 | 3 | 5 | 6 | 7 | 15 |
GPyGMUXn. GPIOz = |
00b, 01b, 10b, 11b | 00b | 01b | 11b | ||||
GPyMUXn. GPIOz = |
00b | 01b | 10b | 11b | 01b | 10b | 11b | 11b |
GPIO0 | EPWM1A (O) | SDAA (I/OD) | ||||||
GPIO1 | EPWM1B (O) | MFSRB (I/O) | SCLA (I/OD) | |||||
GPIO2 | EPWM2A (O) | OUTPUTXBAR1 (O) | SDAB (I/OD) | |||||
GPIO3 | EPWM2B (O) | OUTPUTXBAR2 (O) | MCLKRB (I/O) | OUTPUTXBAR2 (O) | SCLB (I/OD) | |||
GPIO4 | EPWM3A (O) | OUTPUTXBAR3 (O) | CANTXA (O) | |||||
GPIO5 | EPWM3B (O) | MFSRA (I/O) | OUTPUTXBAR3 (O) | CANRXA (I) | ||||
GPIO6 | EPWM4A (O) | OUTPUTXBAR4 (O) | EXTSYNCOUT (O) | EQEP3A (I) | CANTXB (O) | |||
GPIO7 | EPWM4B (O) | MCLKRA (I/O) | OUTPUTXBAR5 (O) | EQEP3B (I) | CANRXB (I) | |||
GPIO8 | EPWM5A (O) | CANTXB (O) | ADCSOCAO (O) | EQEP3S (I/O) | SCITXDA (O) | |||
GPIO9 | EPWM5B (O) | SCITXDB (O) | OUTPUTXBAR6 (O) | EQEP3I (I/O) | SCIRXDA (I) | |||
GPIO10 | EPWM6A (O) | CANRXB (I) | ADCSOCBO (O) | EQEP1A (I) | SCITXDB (O) | UPP-WAIT (I/O) | ||
GPIO11 | EPWM6B (O) | SCIRXDB (I) | OUTPUTXBAR7 (O) | EQEP1B (I) | SCIRXDB (I) | UPP-START (I/O) | ||
GPIO12 | EPWM7A (O) | CANTXB (O) | MDXB (O) | EQEP1S (I/O) | SCITXDC (O) | UPP-ENA (I/O) | ||
GPIO13 | EPWM7B (O) | CANRXB (I) | MDRB (I) | EQEP1I (I/O) | SCIRXDC (I) | UPP-D7 (I/O) | ||
GPIO14 | EPWM8A (O) | SCITXDB (O) | MCLKXB (I/O) | OUTPUTXBAR3 (O) | UPP-D6 (I/O) | |||
GPIO15 | EPWM8B (O) | SCIRXDB (I) | MFSXB (I/O) | OUTPUTXBAR4 (O) | UPP-D5 (I/O) | |||
GPIO16 | SPISIMOA (I/O) | CANTXB (O) | OUTPUTXBAR7 (O) | EPWM9A (O) | SD1_D1 (I) | UPP-D4 (I/O) | ||
GPIO17 | SPISOMIA (I/O) | CANRXB (I) | OUTPUTXBAR8 (O) | EPWM9B (O) | SD1_C1 (I) | UPP-D3 (I/O) | ||
GPIO18 | SPICLKA (I/O) | SCITXDB (O) | CANRXA (I) | EPWM10A (O) | SD1_D2 (I) | UPP-D2 (I/O) | ||
GPIO19 | SPISTEA (I/O) | SCIRXDB (I) | CANTXA (O) | EPWM10B (O) | SD1_C2 (I) | UPP-D1 (I/O) | ||
GPIO20 | EQEP1A (I) | MDXA (O) | CANTXB (O) | EPWM11A (O) | SD1_D3 (I) | UPP-D0 (I/O) | ||
GPIO21 | EQEP1B (I) | MDRA (I) | CANRXB (I) | EPWM11B (O) | SD1_C3 (I) | UPP-CLK (I/O) | ||
GPIO22 | EQEP1S (I/O) | MCLKXA (I/O) | SCITXDB (O) | EPWM12A (O) | SPICLKB (I/O) | SD1_D4 (I) | ||
GPIO23 | EQEP1I (I/O) | MFSXA (I/O) | SCIRXDB (I) | EPWM12B (O) | SPISTEB (I/O) | SD1_C4 (I) | ||
GPIO24 | OUTPUTXBAR1 (O) | EQEP2A (I) | MDXB (O) | SPISIMOB (I/O) | SD2_D1 (I) | |||
GPIO25 | OUTPUTXBAR2 (O) | EQEP2B (I) | MDRB (I) | SPISOMIB (I/O) | SD2_C1 (I) | |||
GPIO26 | OUTPUTXBAR3 (O) | EQEP2I (I/O) | MCLKXB (I/O) | OUTPUTXBAR3 (O) | SPICLKB (I/O) | SD2_D2 (I) | ||
GPIO27 | OUTPUTXBAR4 (O) | EQEP2S (I/O) | MFSXB (I/O) | OUTPUTXBAR4 (O) | SPISTEB (I/O) | SD2_C2 (I) | ||
GPIO28 | SCIRXDA (I) | EM1CS4 (O) | OUTPUTXBAR5 (O) | EQEP3A (I) | SD2_D3 (I) | |||
GPIO29 | SCITXDA (O) | EM1SDCKE (O) | OUTPUTXBAR6 (O) | EQEP3B (I) | SD2_C3 (I) | |||
GPIO30 | CANRXA (I) | EM1CLK (O) | OUTPUTXBAR7 (O) | EQEP3S (I/O) | SD2_D4 (I) | |||
GPIO31 | CANTXA (O) | EM1WE (O) | OUTPUTXBAR8 (O) | EQEP3I (I/O) | SD2_C4 (I) | |||
GPIO32 | SDAA (I/OD) | EM1CS0 (O) | ||||||
GPIO33 | SCLA (I/OD) | EM1RNW (O) | ||||||
GPIO34 | OUTPUTXBAR1 (O) | EM1CS2 (O) | SDAB (I/OD) | |||||
GPIO35 | SCIRXDA (I) | EM1CS3 (O) | SCLB (I/OD) | |||||
GPIO36 | SCITXDA (O) | EM1WAIT (I) | CANRXA (I) | |||||
GPIO37 | OUTPUTXBAR2 (O) | EM1OE (O) | CANTXA (O) | |||||
GPIO38 | EM1A0 (O) | SCITXDC (O) | CANTXB (O) | |||||
GPIO39 | EM1A1 (O) | SCIRXDC (I) | CANRXB (I) | |||||
GPIO40 | EM1A2 (O) | SDAB (I/OD) | ||||||
GPIO41 | EM1A3 (O) | SCLB (I/OD) | ||||||
GPIO42 | SDAA (I/OD) | SCITXDA (O) | ||||||
GPIO43 | SCLA (I/OD) | SCIRXDA (I) | ||||||
GPIO44 | EM1A4 (O) | |||||||
GPIO45 | EM1A5 (O) | |||||||
GPIO46 | EM1A6 (O) | SCIRXDD (I) | ||||||
GPIO47 | EM1A7 (O) | SCITXDD (O) | ||||||
GPIO48 | OUTPUTXBAR3 (O) | EM1A8 (O) | SCITXDA (O) | SD1_D1 (I) | ||||
GPIO49 | OUTPUTXBAR4 (O) | EM1A9 (O) | SCIRXDA (I) | SD1_C1 (I) | ||||
GPIO50 | EQEP1A (I) | EM1A10 (O) | SPISIMOC (I/O) | SD1_D2 (I) | ||||
GPIO51 | EQEP1B (I) | EM1A11 (O) | SPISOMIC (I/O) | SD1_C2 (I) | ||||
GPIO52 | EQEP1S (I/O) | EM1A12 (O) | SPICLKC (I/O) | SD1_D3 (I) | ||||
GPIO53 | EQEP1I (I/O) | EM1D31 (I/O) | EM2D15 (I/O) | SPISTEC (I/O) | SD1_C3 (I) | |||
GPIO54 | SPISIMOA (I/O) | EM1D30 (I/O) | EM2D14 (I/O) | EQEP2A (I) | SCITXDB (O) | SD1_D4 (I) | ||
GPIO55 | SPISOMIA (I/O) | EM1D29 (I/O) | EM2D13 (I/O) | EQEP2B (I) | SCIRXDB (I) | SD1_C4 (I) | ||
GPIO56 | SPICLKA (I/O) | EM1D28 (I/O) | EM2D12 (I/O) | EQEP2S (I/O) | SCITXDC (O) | SD2_D1 (I) | ||
GPIO57 | SPISTEA (I/O) | EM1D27 (I/O) | EM2D11 (I/O) | EQEP2I (I/O) | SCIRXDC (I) | SD2_C1 (I) | ||
GPIO58 | MCLKRA (I/O) | EM1D26 (I/O) | EM2D10 (I/O) | OUTPUTXBAR1 (O) | SPICLKB (I/O) | SD2_D2 (I) | SPISIMOA(3) (I/O) | |
GPIO59 | MFSRA (I/O) | EM1D25 (I/O) | EM2D9 (I/O) | OUTPUTXBAR2 (O) | SPISTEB (I/O) | SD2_C2 (I) | SPISOMIA(3) (I/O) | |
GPIO60 | MCLKRB (I/O) | EM1D24 (I/O) | EM2D8 (I/O) | OUTPUTXBAR3 (O) | SPISIMOB (I/O) | SD2_D3 (I) | SPICLKA(3) (I/O) | |
GPIO61 | MFSRB (I/O) | EM1D23 (I/O) | EM2D7 (I/O) | OUTPUTXBAR4 (O) | SPISOMIB (I/O) | SD2_C3 (I) | SPISTEA(3) (I/O) | |
GPIO62 | SCIRXDC (I) | EM1D22 (I/O) | EM2D6 (I/O) | EQEP3A (I) | CANRXA (I) | SD2_D4 (I) | ||
GPIO63 | SCITXDC (O) | EM1D21 (I/O) | EM2D5 (I/O) | EQEP3B (I) | CANTXA (O) | SD2_C4 (I) | SPISIMOB(3) (I/O) | |
GPIO64 | EM1D20 (I/O) | EM2D4 (I/O) | EQEP3S (I/O) | SCIRXDA (I) | SPISOMIB(3) (I/O) | |||
GPIO65 | EM1D19 (I/O) | EM2D3 (I/O) | EQEP3I (I/O) | SCITXDA (O) | SPICLKB(3) (I/O) | |||
GPIO66 | EM1D18 (I/O) | EM2D2 (I/O) | SDAB (I/OD) | SPISTEB(3) (I/O) | ||||
GPIO67 | EM1D17 (I/O) | EM2D1 (I/O) | ||||||
GPIO68 | EM1D16 (I/O) | EM2D0 (I/O) | ||||||
GPIO69 | EM1D15 (I/O) | SCLB (I/OD) | SPISIMOC(3) (I/O) | |||||
GPIO70 | EM1D14 (I/O) | CANRXA (I) | SCITXDB (O) | SPISOMIC(3) (I/O) | ||||
GPIO71 | EM1D13 (I/O) | CANTXA (O) | SCIRXDB (I) | SPICLKC(3) (I/O) | ||||
GPIO72 | EM1D12 (I/O) | CANTXB (O) | SCITXDC (O) | SPISTEC(3) (I/O) | ||||
GPIO73 | EM1D11 (I/O) | XCLKOUT (O) | CANRXB (I) | SCIRXDC (I) | ||||
GPIO74 | EM1D10 (I/O) | |||||||
GPIO75 | EM1D9 (I/O) | |||||||
GPIO76 | EM1D8 (I/O) | SCITXDD (O) | ||||||
GPIO77 | EM1D7 (I/O) | SCIRXDD (I) | ||||||
GPIO78 | EM1D6 (I/O) | EQEP2A (I) | ||||||
GPIO79 | EM1D5 (I/O) | EQEP2B (I) | ||||||
GPIO80 | EM1D4 (I/O) | EQEP2S (I/O) | ||||||
GPIO81 | EM1D3 (I/O) | EQEP2I (I/O) | ||||||
GPIO82 | EM1D2 (I/O) | |||||||
GPIO83 | EM1D1 (I/O) | |||||||
GPIO84 | SCITXDA (O) | MDXB (O) | MDXA (O) | |||||
GPIO85 | EM1D0 (I/O) | SCIRXDA (I) | MDRB (I) | MDRA (I) | ||||
GPIO86 | EM1A13 (O) | EM1CAS (O) | SCITXDB (O) | MCLKXB (I/O) | MCLKXA (I/O) | |||
GPIO87 | EM1A14 (O) | EM1RAS (O) | SCIRXDB (I) | MFSXB (I/O) | MFSXA (I/O) | |||
GPIO88 | EM1A15 (O) | EM1DQM0 (O) | ||||||
GPIO89 | EM1A16 (O) | EM1DQM1 (O) | SCITXDC (O) | |||||
GPIO90 | EM1A17 (O) | EM1DQM2 (O) | SCIRXDC (I) | |||||
GPIO91 | EM1A18 (O) | EM1DQM3 (O) | SDAA (I/OD) | |||||
GPIO92 | EM1A19 (O) | EM1BA1 (O) | SCLA (I/OD) | |||||
GPIO93 | EM1BA0 (O) | SCITXDD (O) | ||||||
GPIO94 | SCIRXDD (I) | |||||||
GPIO95 | ||||||||
GPIO96 | EM2DQM1 (O) | EQEP1A (I) | ||||||
GPIO97 | EM2DQM0 (O) | EQEP1B (I) | ||||||
GPIO98 | EM2A0 (O) | EQEP1S (I/O) | ||||||
GPIO99 | EM2A1 (O) | EQEP1I (I/O) | ||||||
GPIO100 | EM2A2 (O) | EQEP2A (I) | SPISIMOC (I/O) | |||||
GPIO101 | EM2A3 (O) | EQEP2B (I) | SPISOMIC (I/O) | |||||
GPIO102 | EM2A4 (O) | EQEP2S (I/O) | SPICLKC (I/O) | |||||
GPIO103 | EM2A5 (O) | EQEP2I (I/O) | SPISTEC (I/O) | |||||
GPIO104 | SDAA (I/OD) | EM2A6 (O) | EQEP3A (I) | SCITXDD (O) | ||||
GPIO105 | SCLA (I/OD) | EM2A7 (O) | EQEP3B (I) | SCIRXDD (I) | ||||
GPIO106 | EM2A8 (O) | EQEP3S (I/O) | SCITXDC (O) | |||||
GPIO107 | EM2A9 (O) | EQEP3I (I/O) | SCIRXDC (I) | |||||
GPIO108 | EM2A10 (O) | |||||||
GPIO109 | EM2A11 (O) | |||||||
GPIO110 | EM2WAIT (I) | |||||||
GPIO111 | EM2BA0 (O) | |||||||
GPIO112 | EM2BA1 (O) | |||||||
GPIO113 | EM2CAS (O) | |||||||
GPIO114 | EM2RAS (O) | |||||||
GPIO115 | EM2CS0 (O) | |||||||
GPIO116 | EM2CS2 (O) | |||||||
GPIO117 | EM2SDCKE (O) | |||||||
GPIO118 | EM2CLK (O) | |||||||
GPIO119 | EM2RNW (O) | |||||||
GPIO120 | EM2WE (O) | USB0PFLT | ||||||
GPIO121 | EM2OE (O) | USB0EPEN | ||||||
GPIO122 | SPISIMOC (I/O) | SD1_D1 (I) | ||||||
GPIO123 | SPISOMIC (I/O) | SD1_C1 (I) | ||||||
GPIO124 | SPICLKC (I/O) | SD1_D2 (I) | ||||||
GPIO125 | SPISTEC (I/O) | SD1_C2 (I) | ||||||
GPIO126 | SD1_D3 (I) | |||||||
GPIO127 | SD1_C3 (I) | |||||||
GPIO128 | SD1_D4 (I) | |||||||
GPIO129 | SD1_C4 (I) | |||||||
GPIO130 | SD2_D1 (I) | |||||||
GPIO131 | SD2_C1 (I) | |||||||
GPIO132 | SD2_D2 (I) | |||||||
GPIO133/ AUXCLKIN |
SD2_C2 (I) | |||||||
GPIO134 | SD2_D3 (I) | |||||||
GPIO135 | SCITXDA (O) | SD2_C3 (I) | ||||||
GPIO136 | SCIRXDA (I) | SD2_D4 (I) | ||||||
GPIO137 | SCITXDB (O) | SD2_C4 (I) | ||||||
GPIO138 | SCIRXDB (I) | |||||||
GPIO139 | SCIRXDC (I) | |||||||
GPIO140 | SCITXDC (O) | |||||||
GPIO141 | SCIRXDD (I) | |||||||
GPIO142 | SCITXDD (O) | |||||||
GPIO143 | ||||||||
GPIO144 | ||||||||
GPIO145 | EPWM1A (O) | |||||||
GPIO146 | EPWM1B (O) | |||||||
GPIO147 | EPWM2A (O) | |||||||
GPIO148 | EPWM2B (O) | |||||||
GPIO149 | EPWM3A (O) | |||||||
GPIO150 | EPWM3B (O) | |||||||
GPIO151 | EPWM4A (O) | |||||||
GPIO152 | EPWM4B (O) | |||||||
GPIO153 | EPWM5A (O) | |||||||
GPIO154 | EPWM5B (O) | |||||||
GPIO155 | EPWM6A (O) | |||||||
GPIO156 | EPWM6B (O) | |||||||
GPIO157 | EPWM7A (O) | |||||||
GPIO158 | EPWM7B (O) | |||||||
GPIO159 | EPWM8A (O) | |||||||
GPIO160 | EPWM8B (O) | |||||||
GPIO161 | EPWM9A (O) | |||||||
GPIO162 | EPWM9B (O) | |||||||
GPIO163 | EPWM10A (O) | |||||||
GPIO164 | EPWM10B (O) | |||||||
GPIO165 | EPWM11A (O) | |||||||
GPIO166 | EPWM11B (O) | |||||||
GPIO167 | EPWM12A (O) | |||||||
GPIO168 | EPWM12B (O) |
The Input X-BAR is used to route any GPIO input to the ADC, eCAP, and ePWM peripherals as well as to external interrupts (XINT) (see Figure 3-6). Table 3-4 shows the input X-BAR destinations. For details on configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
INPUT | DESTINATIONS |
---|---|
INPUT1 | EPWM[TZ1,TRIP1], EPWM X-BAR, Output X-BAR |
INPUT2 | EPWM[TZ2,TRIP2], EPWM X-BAR, Output X-BAR |
INPUT3 | EPWM[TZ3,TRIP3], EPWM X-BAR, Output X-BAR |
INPUT4 | XINT1, EPWM X-BAR, Output X-BAR |
INPUT5 | XINT2, ADCEXTSOC, EXTSYNCIN1, EPWM X-BAR, Output X-BAR |
INPUT6 | XINT3, EPWM[TRIP6], EXTSYNCIN2, EPWM X-BAR, Output X-BAR |
INPUT7 | ECAP1 |
INPUT8 | ECAP2 |
INPUT9 | ECAP3 |
INPUT10 | ECAP4 |
INPUT11 | ECAP5 |
INPUT12 | ECAP6 |
INPUT13 | XINT4 |
INPUT14 | XINT5 |
The Output X-BAR has eight outputs which can be selected on the GPIO mux as OUTPUTXBARx. The ePWM X-BAR has eight outputs which are connected to the TRIPx inputs of the ePWM. The sources for both the Output X-BAR and ePWM X-BAR are shown in Figure 3-7. For details on the Output X-BAR and ePWM X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
Table 3-5 shows assignment of the alternate USB function mapping. These can be configured with the GPBAMSEL register.
GPIO | GPBAMSEL SETTING | USB FUNCTION |
---|---|---|
GPIO42 | GPBAMSEL[10] = 1b | USB0DM |
GPIO43 | GPBAMSEL[11] = 1b | USB0DP |
The SPI module on this device has a high-speed mode. To achieve the highest possible speed, a special GPIO configuration is used on a single GPIO mux option for each SPI. These GPIOs may also be used by the SPI when not in high-speed mode (HS_MODE = 0).
To select the mux options that enable the SPI high-speed mode, configure the GPyGMUX and GPyMUX registers as shown in Table 3-6.
GPIO | SPI SIGNAL | MUX CONFIGURATION | |
---|---|---|---|
SPIA | |||
GPIO58 | SPISIMOA | GPBGMUX2[21:20]=11b | GPBMUX2[21:20]=11b |
GPIO59 | SPISOMIA | GPBGMUX2[23:22]=11b | GPBMUX2[23:22]=11b |
GPIO60 | SPICLKA | GPBGMUX2[25:24]=11b | GPBMUX2[25:24]=11b |
GPIO61 | SPISTEA | GPBGMUX2[27:26]=11b | GPBMUX2[27:26]=11b |
SPIB | |||
GPIO63 | SPISIMOB | GPBGMUX2[31:30]=11b | GPBMUX2[31:30]=11b |
GPIO64 | SPISOMIB | GPCGMUX1[1:0]=11b | GPCMUX1[1:0]=11b |
GPIO65 | SPICLKB | GPCGMUX1[3:2]=11b | GPCMUX1[3:2]=11b |
GPIO66 | SPISTEB | GPCGMUX1[5:4]=11b | GPCMUX1[5:4]=11b |
SPIC | |||
GPIO69 | SPISIMOC | GPCGMUX1[11:10]=11b | GPCMUX1[11:10]=11b |
GPIO70 | SPISOMIC | GPCGMUX1[13:12]=11b | GPCMUX1[13:12]=11b |
GPIO71 | SPICLKC | GPCGMUX1[15:14]=11b | GPCMUX1[15:14]=11b |
GPIO72 | SPISTEC | GPCGMUX1[17:16]=11b | GPCMUX1[17:16]=11b |
For applications that do not need to use all functions of the device, Table 3-7 lists acceptable conditioning for any unused pins. When multiple options are listed in Table 3-7, any are acceptable. Pins not listed in Table 3-7 must be connected according to Table 3-1.
SIGNAL NAME | ACCEPTABLE PRACTICE |
---|---|
Analog | |
VREFHIx | Tie to VDDA |
VREFLOx | Tie to VSSA |
ADCINx |
|
Digital | |
GPIOx |
|
X1 | Tie to VSS |
X2 | No Connect |
TCK |
|
TDI |
|
TDO | No Connect |
TMS | No Connect |
TRST | Pulldown resistor (2.2 kΩ or smaller) |
VREGENZ | Tie to VDDIO. VREG is not supported. |
ERRORSTS | No Connect |
FLT1 | No Connect |
FLT2 | No Connect |
Power and Ground | |
VDD | All VDD pins must be connected per Table 3-1. |
VDDA | If a separate analog supply is not used, tie to VDDIO. |
VDDIO | All VDDIO pins must be connected per Table 3-1. |
VDD3VFL | Must be tied to VDDIO |
VDDOSC | Must be tied to VDDIO |
VSS | All VSS pins must be connected to board ground. |
VSSA | If a separate analog ground is not used, tie to VSS. |
VSSOSC | If an external crystal is not used, this pin may be connected to the board ground. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | VDDIO with respect to VSS | –0.3 | 4.6 | V |
VDD3VFL with respect to VSS | –0.3 | 4.6 | ||
VDDOSC with respect to VSS | –0.3 | 4.6 | ||
VDD with respect to VSS | –0.3 | 1.5 | ||
Analog voltage | VDDA with respect to VSSA | –0.3 | 4.6 | V |
Input voltage | VIN (3.3 V) | –0.3 | 4.6 | V |
Output voltage | VO | –0.3 | 4.6 | V |
Input clamp current | Digital input (per pin), IIK (VIN < VSS or VIN > VDDIO) | –20 | 20 | mA |
Analog input (per pin), IIKANALOG
(VIN < VSSA or VIN > VDDA) |
–20 | 20 | ||
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA) |
–20 | 20 | ||
Output current | Digital output (per pin), IOUT | –20 | 20 | mA |
Operating junction temperature | TJ | –55 | 150 | °C |
Storage temperature(3) | Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
TMS320F28377D in 337-ball ZWT package | |||||
V(ESD) | Electrostatic discharge (ESD) | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V | |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | ||||
TMS320F28377D in 176-pin PTP package | |||||
V(ESD) | Electrostatic discharge (ESD) | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V | |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Device supply voltage, I/O, VDDIO(1) | 3.14 | 3.3 | 3.47 | V | |
Device supply voltage, VDD | 1.14 | 1.2 | 1.26 | V | |
Supply ground, VSS | 0 | V | |||
Analog supply voltage, VDDA | 3.14 | 3.3 | 3.47 | V | |
Analog ground, VSSA | 0 | V | |||
Junction temperature, TJ (2) | –55 | 125 | °C |
Current values listed in this section are representative for the test conditions given and not the absolute maximum possible. The actual device currents in an application will vary with application code and pin configurations. Table 4-1 shows the device current consumption at 200-MHz SYSCLK.
MODE | TEST CONDITIONS | IDD | IDDIO(1) | IDDA | IDD3VFL | ||||
---|---|---|---|---|---|---|---|---|---|
TYP(5) | MAX(4) | TYP(5) | MAX(4) | TYP(5) | MAX(4) | TYP(5) | MAX(4) | ||
Operational (RAM) |
|
325 mA | 440 mA | 30 mA | 13 mA | 20 mA | 33 mA | 40 mA | |
IDLE |
|
105 mA | 210 mA | 3 mA | 10 mA | 10 µA | 150 µA | 10 µA | 150 µA |
STANDBY |
|
30 mA | 135 mA | 3 mA | 10 mA | 5 µA | 150 µA | 10 µA | 150 µA |
HALT(2) |
|
1.5 mA | 110 mA | 750 µA | 2 mA | 5 µA | 150 µA | 10 µA | 150 µA |
HIBERNATE(3) |
|
300 µA | 4 mA | 750 µA | 2 mA | 5 µA | 75 µA | 1 µA | 50 µA |
Flash Erase/Program |
|
242 mA | 360 mA | 3 mA | 10 mA | 10 µA | 150 µA | 53 mA | 65 mA |
Figure 4-2 and Figure 4-3 are a typical representation of the relationship between frequency and current consumption/power on the device. The operational test from Table 4-1 was run across frequency at Vmax and high temperature. Actual results will vary based on the system implementation and conditions.
Leakage current will increase with operating temperature in a nonlinear manner. The difference in VDD current between TYP and MAX conditions can be seen in Figure 4-4. The current consumption in HALT mode is primarily leakage current as there is no active switching if the internal oscillator has been powered down.
Figure 4-4 shows the typical leakage current across temperature. The device was placed into HALT mode under nominal voltage conditions.
The F28377D provides some methods to reduce the device current consumption:
PERIPHERAL MODULE(2) |
IDD CURRENT REDUCTION (mA) |
---|---|
ADC(3) | 3.3 |
CAN | 3.3 |
CLA | 1.4 |
CMPSS(3) | 1.4 |
CPUTIMER | 0.3 |
DAC(3) | 0.6 |
DMA | 2.9 |
eCAP | 0.6 |
EMIF1 | 2.9 |
EMIF2 | 2.6 |
ePWM1 to ePWM4(4) | 4.5 |
ePWM5 to ePWM12(4) | 1.7 |
HRPWM(4) | 1.7 |
I2C | 1.3 |
McBSP | 1.6 |
SCI | 0.9 |
SDFM | 2 |
SPI | 0.5 |
uPP | 7.3 |
USB and AUXPLL at 60 MHz | 23.8 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = IOH MIN | VDDIO * 0.8 | V | |||
IOH = –100 μA | VDDIO – 0.2 | ||||||
VOL | Low-level output voltage | IOL = IOL MAX | 0.4 | V | |||
IOL = 100 µA | 0.2 | ||||||
IOH | High-level output source current for all output pins | –4 | mA | ||||
IOL | Low-level output sink current for all output pins | 4 | mA | ||||
VIH | High-level input voltage (3.3 V) | GPIO0–GPIO7, GPIO42–GPIO43, GPIO46–GPIO47 |
VDDIO * 0.7 | VDDIO + 0.3 | V | ||
All other pins | 2.0 | VDDIO + 0.3 | |||||
VIL | Low-level input voltage (3.3 V) | VSS – 0.3 | 0.8 | V | |||
Ipulldown | Input current | Digital inputs with pulldown(1) | VDDIO = 3.3 V VIN = VDDIO |
120 | µA | ||
Ipullup | Input current | Digital inputs with pullup enabled(1) | VDDIO = 3.3 V VIN = 0 V |
150 | µA | ||
ILEAK | Pin leakage | Digital | Pullups disabled 0 V ≤ VIN ≤ VDDIO |
2 | µA | ||
Analog (except ADCINB0 or DACOUTx) | 0 V ≤ VIN ≤ VDDA | 2 | |||||
ADCINB0 | 2 | 11(2) | |||||
DACOUTx | 66 | ||||||
CI | Input capacitance | 2 | pF |
°C/W(1) | AIR FLOW (lfm)(2) | ||
---|---|---|---|
RΘJC | Junction-to-case thermal resistance | 8.8 | N/A |
RΘJB | Junction-to-board thermal resistance | 11.6 | N/A |
RΘJA (High k PCB) | Junction-to-free air thermal resistance | 23.2 | 0 |
RΘJMA | Junction-to-moving air thermal resistance | 19.0 | 150 |
17.8 | 250 | ||
16.5 | 500 | ||
PsiJT | Junction-to-package top | 0.2 | 0 |
0.3 | 150 | ||
0.4 | 250 | ||
0.5 | 500 | ||
PsiJB | Junction-to-board | 11.4 | 0 |
11.3 | 150 | ||
11.2 | 250 | ||
11.0 | 500 |
°C/W(1) | AIR FLOW (lfm)(2) | ||
---|---|---|---|
RΘJC | Junction-to-case thermal resistance | 10.2 | N/A |
RΘJB | Junction-to-board thermal resistance | 7.9 | N/A |
RΘJA (High k PCB) | Junction-to-free air thermal resistance | 19.4 | 0 |
RΘJMA | Junction-to-moving air thermal resistance | 12.8 | 150 |
11.4 | 250 | ||
10.1 | 500 | ||
PsiJT | Junction-to-package top | 0.11 | 0 |
0.24 | 150 | ||
0.33 | 250 | ||
0.42 | 500 | ||
PsiJB | Junction-to-board | 6.1 | 0 |
5.5 | 150 | ||
5.4 | 250 | ||
5.3 | 500 |
An external power supply must be used to supply 3.3 V to VDDIO, VDD3VFL, VDDOSC, and VDDA and to provide 1.2 V to VDD. The internal VREG is not supported; therefore, the VREGENZ pin must be tied high to 3.3 V. The supplies should ramp to full rail within 10 ms. Table 4-3 shows the supply ramp rate.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply ramp rate | VDDIO, VDD, VDDA, VDD3VFL, VDDOSC with respect to VSS | 330 | 105 | V/s |
The voltage on VDDIO should be greater than VDD or no less than 0.3 V below VDD at all times. VDDIO, VDD3VFL, VDDOSC, and VDDA should be powered up together and be kept within 0.3 V of each other during operation. Before powering the device, no voltage larger than 0.3 V above VDDIO should be applied to any digital pin, and no voltage larger than 0.3 V above VDDA should be applied to any analog pin. The VREFHI voltage should not exceed VDDA at any time.
An internal power-on-reset (POR) circuit holds the device in reset and keeps the I/Os in a high-impedance state during power up. External supply voltage supervisors (SVS) can be used to monitor the voltage on the 3.3-V and 1.2-V rails and drive XRS low should supplies fall outside operational specifications.
XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI watchdog reset also drives the pin low. An external circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. A capacitor should be placed between XRS and VSS for noise filtering; the capacitance should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Figure 4-5 shows the recommended reset circuit.
The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRS low. Use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset sources do not drive XRS; therefore, the pins used for boot mode should not be actively driven by other devices in the system. The boot configuration has a provision for changing the boot pins in OTP; for more details, see the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
Table 4-4 shows the reset (XRS) timing requirements. Table 4-5 shows the reset (XRS) switching characteristics. Figure 4-6 shows the power-on reset. Figure 4-7 shows the warm reset.
MIN | MAX | UNIT | ||
---|---|---|---|---|
th(boot-mode) | Hold time for boot-mode pins | 1.5 | ms | |
tw(RSL2) | Pulse duration, XRS low on warm reset | 3.2 | µs |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
tw(RSL1) | Pulse duration, XRS driven low by device after supplies are stable | 100 | µs | ||
tw(WDRS) | Pulse duration, reset pulse generated by watchdog | 512tc(OSCCLK) | cycles |
Table 4-6 lists four possible clock sources. Figure 4-8 provides an overview of the device's clocking system.
CLOCK SOURCE | MODULES CLOCKED | COMMENTS |
---|---|---|
INTOSC1 | Can be used to provide clock for:
|
Internal oscillator 1. Zero-pin overhead 10-MHz internal oscillator. |
INTOSC2(1) | Can be used to provide clock for:
|
Internal oscillator 2. Zero-pin overhead 10-MHz internal oscillator. |
XTAL | Can be used to provide clock for:
|
External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1 pin. |
AUXCLKIN | Can be used to provide clock for:
|
Single-ended 3.3-V level clock source. GPIO133/AUXCLKIN pin should be used to provide the input clock. |
This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of the internal clocks, and the frequency and switching characteristics of the output clock.
Table 4-7 shows the frequency requirements for the input clocks. Table 4-16 shows the crystal equivalent series resistance requirements. Table 4-8 shows the X1 input level characteristics when using an external clock source. Table 4-9 and Table 4-10 show the timing requirements for the input clocks. Table 4-11 shows the PLL lock times for the Main PLL and the USB PLL.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
f(XTAL) | Frequency, X1/X2, from external crystal or resonator | 10 | 20 | MHz | |
f(X1) | Frequency, X1, from external oscillator (PLL enabled) | 2 | 25 | MHz | |
Frequency, X1, from external oscillator (PLL disabled) | 2 | 100 | MHz | ||
f(AUXI) | Frequency, AUXCLKIN, from external oscillator | 2 | 60 | MHz |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
X1 VIL | Valid low-level input voltage | –0.3 | 0.3 * VDDIO | V |
X1 VIH | Valid high-level input voltage | 0.7 * VDDIO | VDDIO + 0.3 | V |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tf(X1) | Fall time, X1 | 6 | ns | ||
tr(X1) | Rise time, X1 | 6 | ns | ||
tw(X1L) | Pulse duration, X1 low as a percentage of tc(X1) | 45% | 55% | ||
tw(X1H) | Pulse duration, X1 high as a percentage of tc(X1) | 45% | 55% |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tf(AUXI) | Fall time, AUXCLKIN | 6 | ns | ||
tr(AUXI) | Rise time, AUXCLKIN | 6 | ns | ||
tw(AUXL) | Pulse duration, AUXCLKIN low as a percentage of tc(XCI) | 45% | 55% | ||
tw(AUXH) | Pulse duration, AUXCLKIN high as a percentage of tc(XCI) | 45% | 55% |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
t(PLL) | Lock time, Main PLL (X1, from external oscillator) | 50 µs + 2500 * tc(OSCCLK)(1) | µs | ||
t(USB) | Lock time, USB PLL (AUXCLKIN, from external oscillator) | 50 µs + 2500 * tc(OSCCLK)(1) | µs |
Table 4-12 provides the clock frequencies for the internal clocks.
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
f(SYSCLK) | Frequency, device (system) clock | 2 | 200(3) | MHz | |
tc(SYSCLK) | Period, device (system) clock | 5(3) | 500 | ns | |
f(PLLRAWCLK) | Frequency, system PLL output (before SYSCLK divider) | 120 | 400 | MHz | |
f(AUXPLLRAWCLK) | Frequency, auxiliary PLL output (before AUXCLK divider) | 120 | 400 | MHz | |
f(AUXPLL) | Frequency, AUXPLLCLK | 2 | 60 | 60 | MHz |
f(PLL) | Frequency, PLLSYSCLK | 2 | 200(3) | MHz | |
f(LSP) | Frequency, LSPCLK(1) | 2 | 200(3) | MHz | |
tc(LSPCLK) | Period, LSPCLK | 5(3) | 500 | ns | |
f(OSCCLK) | Frequency, OSCCLK (INTOSC1 or INTOSC2 or XTAL or X1) | See respective clock | MHz | ||
f(EPWM) | Frequency, EPWMCLK(2) | 100 | MHz | ||
f(HRPWM) | Frequency, HRPWMCLK | 60 | 100 | MHz |
Table 4-13 provides the frequency of the output clock. Table 4-14 shows the switching characteristics of the output clock, XCLKOUT.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
f(XCO) | Frequency, XCLKOUT | 50 | MHz |
PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
tf(XCO) | Fall time, XCLKOUT | 5 | ns | ||
tr(XCO) | Rise time, XCLKOUT | 5 | ns | ||
tw(XCOL) | Pulse duration, XCLKOUT low | H – 2 | H + 2 | ns | |
tw(XCOH) | Pulse duration, XCLKOUT high | H – 2 | H + 2 | ns |
In addition to the internal 0-pin oscillators, multiple external clock source options are available. Figure 4-9 shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 (also referred to as XTAL) and AUXCLKIN.
When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to prevent over-driving the crystal (drive level can be found in the crystal data sheet). In higher-frequency applications (10 MHz or greater), RD is generally not required. If a damping resistor is required, RD should be as small as possible because the size of the resistance affects start-up time (smaller RD = faster start-up time). TI recommends that the crystal manufacturer characterize the crystal with the application board. Table 4-15 shows the crystal oscillator parameters. Table 4-16 shows the crystal equivalent series resistance (ESR) requirements. Table 4-17 shows the crystal oscillator electrical characteristics.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
CL1, CL2 | Load capacitance | 12 | 24 | pF | |
C0 | Crystal shunt capacitance | 7 | pF |
CRYSTAL FREQUENCY (MHz) | MAXIMUM ESR (Ω) (CL1 = CL2 = 12 pF) |
MAXIMUM ESR (Ω) (CL1 = CL2 = 24 pF) |
---|---|---|
10 | 55 | 110 |
12 | 50 | 95 |
14 | 50 | 90 |
16 | 45 | 75 |
18 | 45 | 65 |
20 | 45 | 50 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Start-up time(1) | f = 20 MHz ESR MAX = 50 Ω CL1 = CL2 = 24 pF C0 = 7 pF |
2 | ms | |||
Crystal drive level (DL) | 1 | mW |
To reduce production board costs and application development time, the F28377D contains two independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, both oscillators are enabled at power up. INTOSC2 is set as the source for the system reference clock (OSCCLK) and INTOSC1 is set as the backup clock source. INTOSC1 can also be manually configured as the system reference clock (OSCCLK). Table 4-18 provides the electrical characteristics of the internal oscillators to determine if this module meets the clocking requirements of the application.
Table 4-18 provides the electrical characteristics of the two internal oscillators.
NOTE
This oscillator cannot be used as the PLL source if the PLLSYSCLK is configured to frequencies above 194 MHz.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
f(INTOSC) | Frequency, INTOSC1 and INTOSC2 | 9.7 | 10.0 | 10.3 | MHz | |
f(INTOSC-STABILITY) | Frequency stability at room temperature | 30ºC, Nominal VDD | ±0.1% | |||
Frequency stability over VDD | 30ºC | ±0.2% | ||||
Frequency stability | –3.0% | 3.0% | ||||
f(INTOSC-ST) | Start-up and settling time | 20 | µs |
The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash through 128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal to execution from RAM. Factoring in discontinuities, most applications will run with an efficiency of approximately 80% relative to code executing from RAM. This flash efficiency lets designers realize a 2× improvement in performance when migrating from the previous generation Delfino MCUs.
This device also has an OTP (One-Time-Programmable) sector used for the dual code security module (DCSM), which cannot be erased after it is programmed.
Table 4-19 shows the minimum required flash wait states at different frequencies. Table 4-20 shows the flash parameters.
CPUCLK (MHz) | MINIMUM WAIT STATES (1) | |
---|---|---|
EXTERNAL OSCILLATOR OR CRYSTAL | INTOSC1 OR INTOSC2 | |
150 < CPUCLK ≤ 200 | 145 < CPUCLK ≤ 194 | 3 |
100 < CPUCLK ≤ 150 | 97 < CPUCLK ≤ 145 | 2 |
50 < CPUCLK ≤ 100 | 48 < CPUCLK ≤ 97 | 1 |
CPUCLK ≤ 50 | CPUCLK ≤ 48 | 0 |
PARAMETER | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
Program Time(1) | 128 data bits + 16 ECC bits | 40 | 300 | µs | ||
8KW sector | 90 | 180 | ms | |||
32KW sector | 360 | 720 | ms | |||
Erase Time(2) at < 25 cycles | 8KW sector | 25 | 50 | ms | ||
32KW sector | 30 | 55 | ||||
Erase Time(2) at 50k cycles | 8KW sector | 105 | 4000 | ms | ||
32KW sector | 110 | 4000 | ||||
Nwec | Write/erase cycles | 20000 | cycles | |||
tretention | Data retention duration at TJ = 85°C | 20 | years |
NOTE
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit word may only be programmed once per write/erase cycle. For more details, see the "Flash: Minimum Programming Word Size" advisory in the TMS320F2837xD Dual-Core Delfino™ MCUs Silicon Errata.
The JTAG port has five dedicated pins: TRST, TMS, TDI, TDO, and TCK. The TRST signal should always be pulled down through a 2.2-kΩ pulldown resistor on the board. This MCU does not support the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These signals should always be pulled up at the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to 4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
See Figure 4-10 to see how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 4-11 shows how to connect to the 20-pin header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are not used and should be grounded.
The PD (Power Detect) terminal of the emulator header should be connected to the board 3.3-V supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should also be connected to board ground. The JTAG clock should be looped from the header TCK output terminal back to the RTCK input terminal of the header (to sense clock continuity by the emulator). Header terminal RESET is an open-drain output from the emulator header that enables board components to be reset through emulator commands (available only through the 20-pin header).
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG header is smaller than 6 in (15.24 cm), and no other devices are present on the JTAG chain. Otherwise, each signal should be buffered. Additionally, for most emulator operations at 10 MHz, no series resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω resistors should be placed in series on each JTAG signal.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints for C28x in CCS.
For more information about JTAG emulation, see the XDS Target Connection Guide.
Table 4-21 lists the JTAG timing requirements. Table 4-22 lists the JTAG switching characteristics. Figure 4-12 shows the JTAG timing.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | tc(TCK) | Cycle time, TCK | 66.66 | ns | |
1a | tw(TCKH) | Pulse duration, TCK high (40% of tc) | 26.66 | ns | |
1b | tw(TCKL) | Pulse duration, TCK low (40% of tc) | 26.66 | ns | |
3 | tsu(TDI-TCKH) | Input setup time, TDI valid to TCK high | 13 | ns | |
tsu(TMS-TCKH) | Input setup time, TMS valid to TCK high | 13 | ns | ||
4 | th(TCKH-TDI) | Input hold time, TDI valid from TCK high | 7 | ns | |
th(TCKH-TMS) | Input hold time, TMS valid from TCK high | 7 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
2 | td(TCKL-TDO) | Delay time, TCK low to TDO valid | 6 | 25 | ns |
The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to a GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input X-BAR which is used to route signals from any GPIO input to different IP blocks such as the ADC(s), eCAP(s), ePWM(s), and external interrupts. For more details, see the X-BAR chapter in the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
Table 4-23 shows the general-purpose output switching characteristics. Figure 4-13 shows the general-purpose output timing.
PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
tr(GPO) | Rise time, GPIO switching low to high | All GPIOs | 8(1) | ns | |
tf(GPO) | Fall time, GPIO switching high to low | All GPIOs | 8(1) | ns | |
tfGPO | Toggling frequency, GPO pins | 25 | MHz |
Table 4-24 shows the general-purpose input timing requirements. Figure 4-14 shows the sampling mode.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tw(SP) | Sampling period | QUALPRD = 0 | 1tc(SYSCLK) | cycles | |
QUALPRD ≠ 0 | 2tc(SYSCLK) * QUALPRD | cycles | |||
tw(IQSW) | Input qualifier sampling window | tw(SP) * (n(1) – 1) | cycles | ||
tw(GPI) (2) | Pulse duration, GPIO low/high | Synchronous mode | 2tc(SYSCLK) | cycles | |
With input qualifier | tw(IQSW) + tw(SP) + 1tc(SYSCLK) | cycles |
The following section summarizes the sampling window width for input signals for various input qualifier configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
In Equation 1, Equation 2, and Equation 3, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
Figure 4-15 shows the general-purpose input timing.
Figure 4-16 provides a high-level view of the interrupt architecture.
As shown in Figure 4-16, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto any of the GPIO pins.
In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt groups, with 16 interrupts per group.
Table 4-25 lists the external interrupt timing requirements. Table 4-26 lists the external interrupt switching characteristics. Figure 4-17 shows the external interrupt timing.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tw(INT) | Pulse duration, INT input low/high | Synchronous | 2tc(SYSCLK) | cycles | |
With qualifier | tw(IQSW) + tw(SP) + 1tc(SYSCLK) | cycles |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
td(INT) | Delay time, INT low/high to interrupt-vector fetch(2) | tw(IQSW) + 14tc(SYSCLK) | tw(IQSW) + tw(SP) + 14tc(SYSCLK) | cycles |
This device has three clock-gating low-power modes and a special power-gating mode.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low Power Modes section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
IDLE, STANDBY, and HALT modes on this device are similar to those on other C28x devices. Table 4-27 describes the effect on the system when any of the clock-gating low-power modes are entered.
MODULES/ CLOCK DOMAIN |
CPU1 IDLE | CPU1 STANDBY | CPU2 IDLE | CPU2 STANDBY | HALT |
---|---|---|---|---|---|
CPU1.CLKIN | Active | Gated | N/A | N/A | Gated |
CPU1.SYSCLK | Active | Gated | N/A | N/A | Gated |
CPU1.CPUCLK | Gated | Gated | N/A | N/A | Gated |
CPU2.CLKIN | N/A | N/A | Active | Gated | Gated |
CPU2.SYSCLK | N/A | N/A | Active | Gated | Gated |
CPU2.CPUCLK | N/A | N/A | Gated | Gated | Gated |
Clock to modules Connected to PERx.SYSCLK | Active | Gated if CPUSEL.PERx = CPU1 | Active | Gated if CPUSEL.PERx = CPU2 | Gated |
CPU1.WDCLK | Active | Active | N/A | N/A | Gated if CLKSRCCTL1.WDHALTI = 0 |
CPU2.WDCLK | N/A | N/A | Active | Active | Gated |
AUXPLLCLK | Active | Active | Active | Active | Gated |
PLL | Powered | Powered | Powered | Powered | Software must power down PLL before entering HALT |
INTOSC1 | Powered | Powered | Powered | Powered | Powered down if CLKSRCCTL1.WDHALTI = 0 |
INTOSC2 | Powered | Powered | Powered | Powered | Powered down if CLKSRCCTL1.WDHALTI = 0 |
Flash | Powered | Powered | Powered | Powered | Software-Controlled |
X1/X2 Crystal Oscillator | Powered | Powered | Powered | Powered | Powered-Down |
HIBERNATE mode is the lowest power mode on this device. It is a global low-power mode that gates the supply voltages to most of the system. HIBERNATE is essentially a controlled power-down with remote wakeup capability, and can be used to save power during long periods of inactivity. Table 4-28 describes the effects on the system when the HIBERNATE mode is entered.
MODULES/POWER DOMAINS | HIBERNATE |
---|---|
M0 and M1 memories | ● Remain on with memory retention if LPMCR.M0M1MODE = 0x00 ● Are off when LPMCR.M0M1MODE = 0x01 |
CPU1, CPU2 digital peripherals | Powered down |
Dx, LSx, GSx memories | Power down, memory contents are lost |
I/Os | On with output state preserved |
Oscillators, PLL, analog peripherals, Flash | Enters Low-Power Mode |
Table 4-29 shows the IDLE mode timing requirements, Table 4-30 shows the switching characteristics, and Figure 4-18 shows the timing diagram for IDLE mode.
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
tw(WAKE) | Pulse duration, external wake-up signal | Without input qualifier | 2tc(SYSCLK) | cycles | ||
With input qualifier | 2tc(SYSCLK) + tw(IQSW) |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
td(WAKE-IDLE) | Delay time, external wake signal to program execution resume (2) | cycles | |||
|
Without input qualifier | 40tc(SYSCLK) | |||
With input qualifier | 40tc(SYSCLK) + tw(WAKE) | ||||
|
Without input qualifier | 6700tc(SYSCLK)(3) | |||
With input qualifier | 6700tc(SYSCLK)(3) + tw(WAKE) | ||||
|
Without input qualifier | 25tc(SYSCLK) | |||
With input qualifier | 25tc(SYSCLK) + tw(WAKE) |
Table 4-31 shows the STANDBY mode timing requirements, Table 4-32 shows the switching characteristics, and Figure 4-19 shows the timing diagram for STANDBY mode.
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
tw(WAKE-INT) | Pulse duration, external wake-up signal | QUALSTDBY = 0 | 2tc(OSCCLK) | 3tc(OSCCLK) | cycles | ||
QUALSTDBY > 0 | (2 + QUALSTDBY)tc(OSCCLK)(1) |
(2 + QUALSTDBY) * tc(OSCCLK) |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
td(IDLE-XCOS) | Delay time, IDLE instruction executed to XCLKOUT stop | 16tc(INTOSC1) | cycles | ||
td(WAKE-STBY) | Delay time, external wake signal to program execution resume(1) | cycles | |||
|
175tc(SYSCLK) + tw(WAKE-INT) | ||||
|
6700tc(SYSCLK)(2) + tw(WAKE-INT) | ||||
|
3tc(OSC) + 15tc(SYSCLK) + tw(WAKE-INT) |
Table 4-33 shows the HALT mode timing requirements, Table 4-34 shows the switching characteristics, and Figure 4-20 shows the timing diagram for HALT mode.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tw(WAKE-GPIO) | Pulse duration, GPIO wake-up signal(1) | toscst + 2tc(OSCCLK) | cycles | ||
tw(WAKE-XRS) | Pulse duration, XRS wake-up signal(1) | toscst + 8tc(OSCCLK) | cycles |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
td(IDLE-XCOS) | Delay time, IDLE instruction executed to XCLKOUT stop | 16tc(INTOSC1) | cycles | |
td(WAKE-HALT) | Delay time, external wake signal end to CPU1 program execution resume | cycles | ||
|
75tc(OSCCLK) | |||
|
17500tc(OSCCLK) (1) | |||
|
75tc(OSCCLK) |
NOTE
CPU2 should enter IDLE mode before CPU1 puts the device into HALT mode. CPU1 should verify that CPU2 has entered IDLE mode using the LPMSTAT register before calling the IDLE instruction to enter HALT.
Table 4-35 shows the HIBERNATE mode timing requirements, Table 4-36 shows the switching characteristics, and Figure 4-21 shows the timing diagram for HIBERNATE mode.
MIN | MAX | UNIT | ||
---|---|---|---|---|
tw(HIBWAKE) | Pulse duration, HIBWAKE signal | 40 | µs | |
tw(WAKEXRS) | Pulse duration, XRS wake-up signal | 40 | µs |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
td(IDLE-XCOS) | Delay time, IDLE instruction executed to XCLKOUT stop | 30tc(SYSCLK) | cycles | |
td(WAKE-HIB) | Delay time, external wake signal to lORestore function start | 1.5 | ms |
NOTE
NOTE
For applications using both CPU1 and CPU2, TI recommends that the application puts CPU2 in either IDLE or STANDBY before entering HIBERNATE mode. If any GPIOs are used and the state is to be preserved, data can be stored in M0/M1 memory of CPU1 to be reconfigured upon wakeup. This should be done before step A of Figure 4-21.
The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous memories (SRAM, NOR flash) or synchronous memory (SDRAM).
The EMIF supports asynchronous memories:
There is an external wait input that allows slower asynchronous memories to extend the memory access. The EMIF module supports up to three chip selects (EMIF_CS[4:2]). Each chip select has the following individually programmable attributes:
The EMIF memory controller is compliant with the JESD21-C SDR SDRAMs that use a 32-bit or 16-bit data bus. The EMIF has a single SDRAM chip select (EMIF_CS[0]).
The address space of the EMIF, for the synchronous memory (SDRAM), lies beyond the 22-bit range of the program address bus and can only be accessed through the data bus, which places a restriction on the C compiler being able to work effectively on data in this space. Therefore, when using SDRAM, the user is advised to copy data (using the DMA) from external memory to RAM before working on it. See the examples in controlSUITE™ (CONTROLSUITE) and the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
SDRAM configurations supported are:
Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. Self-refresh mode allows the SDRAM to be put in a low-power state while still retaining memory contents because the SDRAM will continue to refresh itself even without clocks from the microcontroller. Power-down mode achieves even lower power, except the microcontroller must periodically wake up and issue refreshes if data retention is required. The EMIF module does not support mobile SDRAM devices.
On this device, the EMIF does not support burst access for SDRAM configurations. This means every access to an external SDRAM device will have CAS latency.
Table 4-37 shows the EMIF asynchronous memory timing requirements. Table 4-38 shows the EMIF asynchronous memory switching characteristics. Figure 4-22 through Figure 4-25 show the EMIF asynchronous memory timing diagrams.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
Reads and Writes | |||||
E | EMIF clock period | tc(SYSCLK) | ns | ||
2 | tw(EM_WAIT) | Pulse duration, EMxWAIT assertion and deassertion | 2E | ns | |
Reads | |||||
12 | tsu(EMDV-EMOEH) | Setup time, EMxD[y:0] valid before EMxOE high | 15 | ns | |
13 | th(EMOEH-EMDIV) | Hold time, EMxD[y:0] valid after EMxOE high | 0 | ns | |
14 | tsu(EMOEL-EMWAIT) | Setup Time, EMxWAIT asserted before end of Strobe Phase(2) | 4E+20 | ns | |
Writes | |||||
28 | tsu(EMWEL-EMWAIT) | Setup Time, EMxWAIT asserted before end of Strobe Phase(2) | 4E+20 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
Reads and Writes | |||||
1 | td(TURNAROUND) | Turn around time | (TA)*E–3 | (TA)*E+2 | ns |
Reads | |||||
3 | tc(EMRCYCLE) | EMIF read cycle time (EW = 0) | (RS+RST+RH+2)*E–3 | (RS+RST+RH+2)*E+2 | ns |
EMIF read cycle time (EW = 1) | (RS+RST+RH+2+ (EWC*16))*E–3 |
(RS+RST+RH+2+ (EWC*16))*E+2 |
ns | ||
4 | tsu(EMCEL-EMOEL) | Output setup time, EMxCS[y:2] low to EMxOE low (SS = 0) | (RS)*E–3 | (RS)*E+2 | ns |
Output setup time, EMxCS[y:2] low to EMxOE low (SS = 1) | –3 | 2 | ns | ||
5 | th(EMOEH-EMCEH) | Output hold time, EMxOE high to EMxCS[y:2] high (SS = 0) | (RH)*E–3 | (RH)*E | ns |
Output hold time, EMxOE high to EMxCS[y:2] high (SS = 1) | –3 | 0 | ns | ||
6 | tsu(EMBAV-EMOEL) | Output setup time, EMxBA[y:0] valid to EMxOE low | (RS)*E–3 | (RS)*E+2 | ns |
7 | th(EMOEH-EMBAIV) | Output hold time, EMxOE high to EMxBA[y:0] invalid | (RH)*E–3 | (RH)*E | ns |
8 | tsu(EMAV-EMOEL) | Output setup time, EMxA[y:0] valid to EMxOE low | (RS)*E–3 | (RS)*E+2 | ns |
9 | th(EMOEH-EMAIV) | Output hold time, EMxOE high to EMxA[y:0] invalid | (RH)*E–3 | (RH)*E | ns |
10 | tw(EMOEL) | EMxOE active low width (EW = 0) | (RST)*E–1 | (RST)*E+1 | ns |
EMxOE active low width (EW = 1) | (RST+(EWC*16))*E–1 | (RST+(EWC*16))*E+1 | ns | ||
11 | td(EMWAITH-EMOEH) | Delay time from EMxWAIT deasserted to EMxOE high | 4E+10 | 5E+15 | ns |
29 | tsu(EMDQMV-EMOEL) | Output setup time, EMxDQM[y:0] valid to EMxOE low | (RS)*E–3 | (RS)*E+2 | ns |
30 | th(EMOEH-EMDQMIV) | Output hold time, EMxOE high to EMxDQM[y:0] invalid | (RH)*E–3 | (RH)*E | ns |
Writes | |||||
15 | tc(EMWCYCLE) | EMIF write cycle time (EW = 0) | (WS+WST+WH+2)*E–3 | (WS+WST+WH+2)*E+1 | ns |
EMIF write cycle time (EW = 1) | (WS+WST+WH+2+ (EWC*16))*E–3 |
(WS+WST+WH+2+ (EWC*16))*E+1 |
ns | ||
16 | tsu(EMCEL-EMWEL) | Output setup time, EMxCS[y:2] low to EMxWE low (SS = 0) | (WS)*E–3 | (WS)*E+1 | ns |
Output setup time, EMxCS[y:2] low to EMxWE low (SS = 1) | –3 | 1 | ns | ||
17 | th(EMWEH-EMCEH) | Output hold time, EMxWE high to EMxCS[y:2] high (SS = 0) | (WH)*E–3 | (WH)*E | ns |
Output hold time, EMxWE high to EMxCS[y:2] high (SS = 1) | –3 | 0 | ns | ||
18 | tsu(EMDQMV-EMWEL) | Output setup time, EMxDQM[y:0] valid to EMxWE low | (WS)*E–3 | (WS)*E+1 | ns |
19 | th(EMWEH-EMDQMIV) | Output hold time, EMxWE high to EMxDQM[y:0] invalid | (WH)*E–3 | (WH)*E | ns |
20 | tsu(EMBAV-EMWEL) | Output setup time, EMxBA[y:0] valid to EMxWE low | (WS)*E–3 | (WS)*E+1 | ns |
21 | th(EMWEH-EMBAIV) | Output hold time, EMxWE high to EMxBA[y:0] invalid | (WH)*E–3 | (WH)*E | ns |
22 | tsu(EMAV-EMWEL) | Output setup time, EMxA[y:0] valid to EMxWE low | (WS)*E–3 | (WS)*E+1 | ns |
23 | th(EMWEH-EMAIV) | Output hold time, EMxWE high to EMxA[y:0] invalid | (WH)*E–3 | (WH)*E | ns |
24 | tw(EMWEL) | EMxWE active low width (EW = 0) |
(WST)*E–1 | (WST)*E+1 | ns |
EMxWE active low width (EW = 1) |
(WST+(EWC*16))*E–1 | (WST+(EWC*16))*E+1 | ns | ||
25 | td(EMWAITH-EMWEH) | Delay time from EMxWAIT deasserted to EMxWE high | 4E+10 | 5E+15 | ns |
26 | tsu(EMDV-EMWEL) | Output setup time, EMxD[y:0] valid to EMxWE low | (WS)*E–3 | (WS)*E+1 | ns |
27 | th(EMWEH-EMDIV) | Output hold time, EMxWE high to EMxD[y:0] invalid | (WH)*E–3 | (WH)*E | ns |
Table 4-39 shows the EMIF synchronous memory timing requirements. Table 4-40 shows the EMIF synchronous memory switching characteristics. Figure 4-26 and Figure 4-27 show the synchronous memory timing diagrams.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
19 | tsu(EMIFDV-EM_CLKH) | Input setup time, read data valid on EMxD[y:0] before EMxCLK rising | 2 | ns | |
20 | th(CLKH-DIV) | Input hold time, read data valid on EMxD[y:0] after EMxCLK rising | 1.5 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | tc(CLK) | Cycle time, EMIF clock EMxCLK | 10 | ns | |
2 | tw(CLK) | Pulse width, EMIF clock EMxCLK high or low | 3 | ns | |
3 | td(CLKH-CSV) | Delay time, EMxCLK rising to EMxCS[y:2] valid | 8 | ns | |
4 | toh(CLKH-CSIV) | Output hold time, EMxCLK rising to EMxCS[y:2] invalid | 1 | ns | |
5 | td(CLKH-DQMV) | Delay time, EMxCLK rising to EMxDQM[y:0] valid | 8 | ns | |
6 | toh(CLKH-DQMIV) | Output hold time, EMxCLK rising to EMxDQM[y:0] invalid | 1 | ns | |
7 | td(CLKH-AV) | Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] valid | 8 | ns | |
8 | toh(CLKH-AIV) | Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] invalid | 1 | ns | |
9 | td(CLKH-DV) | Delay time, EMxCLK rising to EMxD[y:0] valid | 8 | ns | |
10 | toh(CLKH-DIV) | Output hold time, EMxCLK rising to EMxD[y:0] invalid | 1 | ns | |
11 | td(CLKH-RASV) | Delay time, EMxCLK rising to EMxRAS valid | 8 | ns | |
12 | toh(CLKH-RASIV) | Output hold time, EMxCLK rising to EMxRAS invalid | 1 | ns | |
13 | td(CLKH-CASV) | Delay time, EMxCLK rising to EMxCAS valid | 8 | ns | |
14 | toh(CLKH-CASIV) | Output hold time, EMxCLK rising to EMxCAS invalid | 1 | ns | |
15 | td(CLKH-WEV) | Delay time, EMxCLK rising to EMxWE valid | 8 | ns | |
16 | toh(CLKH-WEIV) | Output hold time, EMxCLK rising to EMxWE invalid | 1 | ns | |
17 | td(CLKH-DHZ) | Delay time, EMxCLK rising to EMxD[y:0] tri-stated | 8 | ns | |
18 | toh(CLKH-DLZ) | Output hold time, EMxCLK rising to EMxD[y:0] driving | 1 | ns |
This analog subsystem module is described in this section.
The analog modules on this device include the ADC, temperature sensor, buffered DAC, and CMPSS.
The analog subsystem has the following features:
Figure 4-28 shows the Analog Subsystem Block Diagram for the 337-ball ZWT package. Figure 4-29 shows the Analog Subsystem Block Diagram for the 176-pin PTP package. Figure 4-30 shows the Analog Subsystem Block Diagram for the 100-pin PZP package.
The ADCs on this device are successive approximation (SAR) style ADCs with selectable resolution of either 16 bits or 12 bits. There are multiple ADC modules which allow simultaneous sampling. The ADC wrapper is start-of-conversion (SOC) based [see the SOC Principle of Operation section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
Each ADC has the following features:
Figure 4-31 shows the ADC module block diagram.
Table 4-41 shows the ADC operating conditions for 16-bit differential mode. Table 4-42 shows the ADC characteristics for 16-bit differential mode. Table 4-43 shows the ADC operating conditions for 12-bit single-ended mode. Table 4-44 shows the ADC characteristics for 12-bit single-ended mode. Table 4-45 shows the ADCEXTSOC timing requirements.
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
ADCCLK (derived from PERx.SYSCLK) | 5 | 50 | MHz | ||
Sample window duration (set by ACQPS and PERx.SYSCLK)(1) | 320 | ns | |||
VREFHI | 2.4 | 2.5 or 3.0 | VDDA | V | |
VREFLO | VSSA | 0 | VSSA | V | |
VREFHI – VREFLO | 2.4 | VDDA | V | ||
ADC input conversion range | VREFLO | VREFHI | V | ||
ADC input signal common mode voltage(2)(3) | VREFCM – 50 | VREFCM | VREFCM + 50 | mV |
NOTE
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this level, the VREF internal to the device may be disturbed, which can impact results for other ADC or DAC inputs using the same VREF.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
ADC conversion cycles(1) | 29.6 | 31 | ADCCLKs | ||
Power-up time (after setting ADCPWDNZ to first conversion) | 500 | µs | |||
Gain error | –64 | ±9 | 64 | LSBs | |
Offset error(2) | –16 | ±9 | 16 | LSBs | |
Channel-to-channel gain error | ±6 | LSBs | |||
Channel-to-channel offset error | ±3 | LSBs | |||
ADC-to-ADC gain error | Identical VREFHI and VREFLO for all ADCs | ±6 | LSBs | ||
ADC-to-ADC offset error | Identical VREFHI and VREFLO for all ADCs | ±3 | LSBs | ||
DNL(3) | > –1 | ±0.5 | 1 | LSBs | |
INL | –3 | ±1.5 | 3 | LSBs | |
SNR(4)(11) | VREFHI = 2.5 V, fin = 10 kHz | 87.6 | dB | ||
THD(4)(11) | VREFHI = 2.5 V, fin = 10 kHz | –93.5 | dB | ||
SFDR(4)(11) | VREFHI = 2.5 V, fin = 10 kHz | 95.4 | dB | ||
SINAD(4)(11) | VREFHI = 2.5 V, fin = 10 kHz | 86.6 | dB | ||
ENOB(4)(11) | VREFHI = 2.5 V, fin = 10 kHz, single ADC(7) |
14.1 | bits | ||
VREFHI = 2.5 V, fin = 10 kHz, synchronous ADCs(8) | 14.1 | ||||
VREFHI = 2.5 V, fin = 10 kHz, asynchronous ADCs(9) | Not supported | ||||
PSRR | VDDA = 3.3-V DC + 200 mV DC up to Sine at 1 kHz |
77 | dB | ||
PSRR | VDDA = 3.3-V DC + 200 mV Sine at 800 kHz |
74 | dB | ||
CMRR | DC to 1 MHz | 60 | dB | ||
VREFHI input current | 190 | µA | |||
ADC-to-ADC isolation(11)(5)(10) | VREFHI = 2.5 V, synchronous ADCs(8) | –2 | 2 | LSBs | |
VREFHI = 2.5 V, asynchronous ADCs(9) | Not supported |
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|
ADCCLK (derived from PERx.SYSCLK) | 5 | 50 | MHz | |
Sample window duration (set by ACQPS and PERx.SYSCLK)(1) | 75 | ns | ||
VREFHI | 2.4 | 2.5 or 3.0 | VDDA | V |
VREFLO | VSSA | 0 | VSSA | V |
VREFHI – VREFLO | 2.4 | VDDA | V | |
ADC input conversion range | VREFLO | VREFHI | V |
NOTE
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this level, the VREF internal to the device may be disturbed, which can impact results for other ADC or DAC inputs using the same VREF.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
ADC conversion cycles(1) | 10.1 | 11 | ADCCLKs | ||
Power-up time | 500 | µs | |||
Gain error | –5 | ±3 | 5 | LSBs | |
Offset error | –4 | ±2 | 4 | LSBs | |
Channel-to-channel gain error | ±4 | LSBs | |||
Channel-to-channel offset error | ±2 | LSBs | |||
ADC-to-ADC gain error | Identical VREFHI and VREFLO for all ADCs | ±4 | LSBs | ||
ADC-to-ADC offset error | Identical VREFHI and VREFLO for all ADCs | ±2 | LSBs | ||
DNL(2) | > –1 | ±0.5 | 1 | LSBs | |
INL | –2 | ±1.0 | 2 | LSBs | |
SNR(3)(10) | VREFHI = 2.5 V, fin = 100 kHz | 68.8 | dB | ||
THD(3)(10) | VREFHI = 2.5 V, fin = 100 kHz | –78.4 | dB | ||
SFDR(3)(10) | VREFHI = 2.5 V, fin = 100 kHz | 79.2 | dB | ||
SINAD(3)(10) | VREFHI = 2.5 V, fin = 100 kHz | 68.4 | dB | ||
ENOB(3)(10) | VREFHI = 2.5 V, fin = 100 kHz, single ADC(6), all packages |
11.1 | bits | ||
VREFHI = 2.5 V, fin = 100 kHz, synchronous ADCs(7), all packages | 11.1 | ||||
VREFHI = 2.5 V, fin = 100 kHz, asynchronous ADCs(8), 100-pin PZP package |
Not supported | ||||
VREFHI = 2.5 V, fin = 100 kHz, asynchronous ADCs(8), 176-pin PTP package |
9.7 | ||||
VREFHI = 2.5 V, fin = 100 kHz, asynchronous ADCs(8), 337-ball ZWT package |
10.9 | ||||
PSRR | VDDA = 3.3-V DC + 200 mV DC up to Sine at 1 kHz |
60 | dB | ||
PSRR | VDDA = 3.3-V DC + 200 mV Sine at 800 kHz |
57 | dB | ||
ADC-to-ADC isolation(10)(4)(9) | VREFHI = 2.5 V, synchronous ADCs(7), all packages | –1 | 1 | LSBs | |
VREFHI = 2.5 V, asynchronous ADCs(8), 100-pin PZP package | Not supported | ||||
VREFHI = 2.5 V, asynchronous ADCs(8), 176-pin PTP package | –9 | 9 | |||
VREFHI = 2.5 V, asynchronous ADCs(8), 337-ball ZWT package | –2 | 2 | |||
VREFHI input current | 130 | µA |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tw(INT) | Pulse duration, INT input low/high | Synchronous | 2tc(SYSCLK) | cycles | |
With qualifier | tw(IQSW) + tw(SP) + 1tc(SYSCLK) | cycles |
NOTE
ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to VSSA.
For single-ended operation, the ADC input characteristics are given by Table 4-46 and Figure 4-32.
DESCRIPTION | VALUE (12-BIT MODE) | |
---|---|---|
Cp | Parasitic input capacitance | See Table 4-48 |
Ron | Sampling switch resistance | 425 Ω |
Ch | Sampling capacitor | 14.5 pF |
Rs | Nominal source impedance | 50 Ω |
For differential operation, the ADC input characteristics are given by Table 4-47 and Figure 4-33.
DESCRIPTION | VALUE (16-BIT MODE) | |
---|---|---|
Cp | Parasitic input capacitance | See Table 4-48 |
Ron | Sampling switch resistance | 700 Ω |
Ch | Sampling capacitor | 16.5 pF |
Rs | Nominal source impedance | 50 Ω |
Table 4-48 shows the parasitic capacitance on each channel. Also, enabling a comparator adds approximately 1.4 pF of capacitance on positive comparator inputs and 2.5 pF of capacitance on negative comparator inputs.
ADC CHANNEL | Cp (pF) | |
---|---|---|
COMPARATOR DISABLED | COMPARATOR ENABLED | |
ADCINA0 | 12.9 | N/A |
ADCINA1 | 10.3 | N/A |
ADCINA2 | 5.9 | 7.3 |
ADCINA3 | 6.3 | 8.8 |
ADCINA4 | 5.9 | 7.3 |
ADCINA5 | 6.3 | 8.8 |
ADCINB0(1) | 117.0 | N/A |
ADCINB1 | 10.6 | N/A |
ADCINB2 | 5.9 | 7.3 |
ADCINB3 | 6.2 | 8.7 |
ADCINB4 | 5.2 | N/A |
ADCINB5 | 5.1 | N/A |
ADCINC2 | 5.5 | 6.9 |
ADCINC3 | 5.8 | 8.3 |
ADCINC4 | 5.0 | 6.4 |
ADCINC5 | 5.3 | 7.8 |
ADCIND0 | 5.3 | 6.7 |
ADCIND1 | 5.7 | 8.2 |
ADCIND2 | 5.3 | 6.7 |
ADCIND3 | 5.6 | 8.1 |
ADCIND4 | 4.3 | N/A |
ADCIND5 | 4.3 | N/A |
ADCIN14 | 8.6 | 10.0 |
ADCIN15 | 9.0 | 11.5 |
These input models should be used along with actual signal source impedance to determine the acquisition window duration. See the Choosing an Acquisition Window Duration section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more information.
The user should analyze the ADC input setting assuming worst-case initial conditions on Ch. This will require assuming that Ch could start the S+H window completely charged to VREFHI or completely discharged to VREFLO. When the ADC transitions from an odd-numbered channel to an even-numbered channel, or vice-versa, the actual initial voltage on Ch will be close to being completely discharged to VREFLO. For even-to-even or odd-to-odd channel transitions, the initial voltage on Ch will be close to the voltage of the previously converted channel.
Table 4-49 shows the ADC timings in 12-bit mode (SYSCLK cycles). Table 4-50 shows the ADC timings in 16-bit mode. Figure 4-34 and Figure 4-35 show the ADC conversion timings for two SOCs given the following assumptions:
The following parameters are identified in the timing diagrams:
ADCCLK PRESCALE | SYSCLK CYCLES | ADCCLK CYCLES | ||||
---|---|---|---|---|---|---|
ADCCTL2 [PRESCALE] |
RATIO ADCCLK:SYSCLK |
tEOC | tLAT | tINT(EARLY) | tINT(LATE) | tEOC |
0 | 1 | 11 | 13 | 1 | 11 | 11.0 |
1 | 1.5 | Invalid | ||||
2 | 2 | 21 | 23 | 1 | 21 | 10.5 |
3 | 2.5 | 26 | 28 | 1 | 26 | 10.4 |
4 | 3 | 31 | 34 | 1 | 31 | 10.3 |
5 | 3.5 | 36 | 39 | 1 | 36 | 10.3 |
6 | 4 | 41 | 44 | 1 | 41 | 10.3 |
7 | 4.5 | 46 | 49 | 1 | 46 | 10.2 |
8 | 5 | 51 | 55 | 1 | 51 | 10.2 |
9 | 5.5 | 56 | 60 | 1 | 56 | 10.2 |
10 | 6 | 61 | 65 | 1 | 61 | 10.2 |
11 | 6.5 | 66 | 70 | 1 | 66 | 10.2 |
12 | 7 | 71 | 76 | 1 | 71 | 10.1 |
13 | 7.5 | 76 | 81 | 1 | 76 | 10.1 |
14 | 8 | 81 | 86 | 1 | 81 | 10.1 |
15 | 8.5 | 86 | 91 | 1 | 86 | 10.1 |
ADCCLK PRESCALE | SYSCLK CYCLES | ADCCLK CYCLES | ||||
---|---|---|---|---|---|---|
ADCCTL2 [PRESCALE] |
RATIO ADCCLK:SYSCLK |
tEOC | tLAT | tINT(EARLY) | tINT(LATE) | tEOC |
0 | 1 | 31 | 32 | 1 | 31 | 31.0 |
1 | 1.5 | Invalid | ||||
2 | 2 | 60 | 61 | 1 | 60 | 30.0 |
3 | 2.5 | 75 | 75 | 1 | 75 | 30.0 |
4 | 3 | 90 | 91 | 1 | 90 | 30.0 |
5 | 3.5 | 104 | 106 | 1 | 104 | 29.7 |
6 | 4 | 119 | 120 | 1 | 119 | 29.8 |
7 | 4.5 | 134 | 134 | 1 | 134 | 29.8 |
8 | 5 | 149 | 150 | 1 | 149 | 29.8 |
9 | 5.5 | 163 | 165 | 1 | 163 | 29.6 |
10 | 6 | 178 | 179 | 1 | 178 | 29.7 |
11 | 6.5 | 193 | 193 | 1 | 193 | 29.7 |
12 | 7 | 208 | 209 | 1 | 208 | 29.7 |
13 | 7.5 | 222 | 224 | 1 | 222 | 29.6 |
14 | 8 | 237 | 238 | 1 | 237 | 29.6 |
15 | 8.5 | 252 | 252 | 1 | 252 | 29.6 |
The temperature sensor can be used to measure the device junction temperature. The temperature sensor is sampled through an internal connection to the ADC and translated into a temperature through TI-provided software. When sampling the temperature sensor, the ADC must meet the acquisition time in Table 4-51.
PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|
Temperature accuracy | ±15 | °C | ||
Start-up time (TSNSCTL[ENABLE] to sampling temperature sensor) | 500 | µs | ||
ADC acquisition time | 700 | ns |
Each CMPSS module includes two comparators, two internal voltage reference DACs (CMPSS DACs), two digital glitch filters, and one ramp generator. There are two inputs, CMPINxP and CMPINxN. Each of these inputs will be internally connected to an ADCIN pin. The CMPINxP pin is always connected to the positive input of the CMPSS comparators. CMPINxN can be used instead of the DAC output to drive the negative comparator inputs. There are two comparators, and therefore two outputs from the CMPSS module, which are connected to the input of a digital filter module before being passed on to the Comparator TRIP crossbar and either PWM modules or directly to a GPIO pin. Figure 4-36 shows the CMPSS connectivity on the 337-ball ZWT and 176-pin PTP packages. Figure 4-37 shows CMPSS connectivity on the 100-pin PZP package.
Table 4-52 shows the comparator electrical characteristics. Figure 4-38 shows the CMPSS comparator input referred offset. Figure 4-39 shows the CMPSS comparator hysteresis.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Power-up time (from COMPCTL[COMPDACE] to comparator ready) | 10 | µs | |||
Comparator input (CMPINxx) range | 0 | VDDA | V | ||
Input referred offset error | –20 | 20 | mV | ||
Hysteresis(1) | 1x | 12 | CMPSS DAC LSB | ||
2x | 24 | ||||
3x | 36 | ||||
4x | 48 | ||||
Response time (delay from CMPINx input change to output on ePWM X-BAR or Output X-BAR) | Step response | 21 | 60 | ns | |
Ramp response (1.65 V/µs) | 26 | ||||
Ramp response (8.25 mV/µs) | 30 |
NOTE
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If a CMPSS input exceeds this level, an internal blocking circuit will isolate the internal comparator from the external pin until the external pin voltage returns below VDDA + 0.3 V. During this time, the internal comparator input will be floating and can decay below VDDA within approximately 0.5 µs. After this time, the comparator could begin to output an incorrect result depending on the value of the other comparator input.
Table 4-53 shows the CMPSS DAC static electrical characteristics. Figure 4-40 shows the CMPSS DAC static offset. Figure 4-41 shows the CMPSS DAC static gain. Figure 4-42 shows the CMPSS DAC static linearity.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
CMPSS DAC output range | Internal reference | 0 | VDDA | V | |
External reference | 0 | VDAC | |||
Static offset error(1) | –25 | 25 | mV | ||
Static gain error(1) | –2 | 2 | % of FSR | ||
Static DNL | Endpoint corrected | >–1 | 4 | LSB | |
Static INL | Endpoint corrected | –16 | 16 | LSB | |
Settling time | Settling to 1 LSB after full-scale output change | 1 | µs | ||
Resolution | 12 | bits | |||
CMPSS DAC output disturbance(2) | Error induced by comparator trip or CMPSS DAC code change within the same CMPSS module | –100 | 100 | LSB | |
CMPSS DAC disturbance time(2) | 200 | ns | |||
VDAC reference voltage | When VDAC is reference | 2.4 | 2.5 or 3.0 | VDDA | V |
VDAC load(3) | When VDAC is reference | 6 | kΩ |
The buffered DAC module consists of an internal reference DAC and an analog output buffer that is capable of driving an external load. An integrated pulldown resistor on the DAC output helps to provide a known pin voltage when the output buffer is disabled. This pulldown resistor cannot be disabled and remains as a passive component on the pin, even for other shared pin mux functions. Software writes to the DAC value register can take effect immediately or can be synchronized with PWMSYNC events.
Each buffered DAC has the following features:
The block diagram for the buffered DAC is shown in Figure 4-43.
Table 4-54 shows the buffered DAC electrical characteristics. Figure 4-44 shows the buffered DAC offset. Figure 4-45 shows the buffered DAC gain. Figure 4-46 shows the buffered DAC linearity.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Power-up time (DACOUTEN to DAC output valid) | 10 | µs | |||
Trimmed offset error | Midpoint | –10 | 10 | mV | |
Gain error(2) | –2.5 | 2.5 | % of FSR | ||
DNL(3) | Endpoint corrected | > –1 | 1 | LSB | |
INL | Endpoint corrected | –5 | 5 | LSB | |
DACOUTx settling time | Settling to 2 LSBs after 0.3V-to-3V transition | 2 | µs | ||
Resolution | 12 | bits | |||
Voltage output range(4) | 0.3 | VDDA – 0.3 | V | ||
Capacitive load | Output drive capability | 100 | pF | ||
Resistive load | Output drive capability | 5 | kΩ | ||
RPD | 50 | kΩ | |||
Reference voltage(5) | VDAC or VREFHI | 2.4 | 2.5 or 3.0 | VDDA | V |
Reference load(6) | VDAC or VREFHI | 170 | kΩ | ||
Output noise | Integrated noise from 100 Hz to 100 kHz | 500 | µVrms | ||
Noise density at 10 kHz | 711 | nVrms/√Hz | |||
Glitch energy | 1.5 | V-ns | |||
PSRR(7) | DC up to 1 kHz | 70 | dB | ||
100 kHz | 30 | ||||
SNR | 1020 Hz | 67 | dB | ||
THD | 1020 Hz | –63 | dB | ||
SFDR | 1020 Hz, including harmonics and spurs | 66 | dBc | ||
1020 Hz, including only spurs | 104 |
NOTE
The VDAC pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VDAC pin exceeds this level, a blocking circuit may activate, and the internal value of VDAC may float to 0 V internally, giving improper DAC output.
The eCAP module can be used in systems where accurate timing of external events is important.
Applications for eCAP include:
The eCAP module includes the following features:
The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to GPIO pins through the Output X-BAR to OUTPUTx positions in the GPIO mux. See Section 3.4.2 and Section 3.4.3.
Figure 4-47 shows the block diagram of an eCAP module.
The eCAP module is clocked by PERx.SYSCLK.
The clock enable bits (ECAP1–ECAP6) in the PCLKCR3 register turn off the eCAP module individually (for low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
Table 4-55 shows the eCAP timing requirement and Table 4-56 shows the eCAP switching characteristics.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tw(CAP) | Capture input pulse width | Asynchronous | 2tc(SYSCLK) | cycles | |
Synchronous | 2tc(SYSCLK) | cycles | |||
With input qualifier | 1tc(SYSCLK) + tw(IQSW) | cycles |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
tw(APWM) | Pulse duration, APWMx output high/low | 20 | ns |
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced trip-zone functionality, and global register reload capabilities.
Figure 4-48 shows the signal interconnections with the ePWM. Figure 4-49 shows the ePWM trip input connectivity.
The ePWM and eCAP synchronization chain on the device provides flexibility in partitioning the ePWM and eCAP modules between CPU1 and CPU2 and allows localized synchronization within the modules belonging to the same CPU. Like the other peripherals, the partitioning of the ePWM and eCAP modules needs to be done using the CPUSELx registers. Figure 4-50 shows the synchronization chain architecture.
Table 4-57 shows the PWM timing requirements and Table 4-58 shows the PWM switching characteristics.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tw(SYNCIN) | Sync input pulse width | Asynchronous | 2tc(EPWMCLK) | cycles | |
Synchronous | 2tc(EPWMCLK) | cycles | |||
With input qualifier | 1tc(EPWMCLK) + tw(IQSW) | cycles |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
tw(PWM) | Pulse duration, PWMx output high/low | 20 | ns | |
tw(SYNCOUT) | Sync output pulse width | 8tc(SYSCLK) | cycles | |
td(TZ-PWM) | Delay time, trip input active to PWM forced high Delay time, trip input active to PWM forced low Delay time, trip input active to PWM Hi-Z |
25 | ns |
Table 4-59 shows the trip-zone input timing requirements. Figure 4-51 shows the PWM Hi-Z characteristics.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tw(TZ) | Pulse duration, TZx input low | Asynchronous | 1tc(EPWMCLK) | cycles | |
Synchronous | 2tc(EPWMCLK) | cycles | |||
With input qualifier | 1tc(EPWMCLK) + tw(IQSW) | cycles |
Table 4-60 shows the external ADC start-of-conversion switching characteristics. Figure 4-52 shows the ADCSOCAO or ADCSOCBO timing.
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
tw(ADCSOCL) | Pulse duration, ADCSOCxO low | 32tc(SYSCLK) | cycles |
The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position, direction, and speed information from rotating machines used in high-performance motion and position-control systems.
Each eQEP peripheral comprises five major functional blocks:
The eQEP peripherals are clocked by PERx.SYSCLK. Figure 4-53 shows the eQEP block diagram.
Table 4-61 lists the eQEP timing requirement and Table 4-62 lists the eQEP switching characteristics.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tw(QEPP) | QEP input period | Asynchronous(2)/Synchronous | 2tc(SYSCLK) | cycles | |
With input qualifier | 2[1tc(SYSCLK) + tw(IQSW)] | cycles | |||
tw(INDEXH) | QEP Index Input High time | Asynchronous(2)/Synchronous | 2tc(SYSCLK) | cycles | |
With input qualifier | 2tc(SYSCLK) + tw(IQSW) | cycles | |||
tw(INDEXL) | QEP Index Input Low time | Asynchronous(2)/Synchronous | 2tc(SYSCLK) | cycles | |
With input qualifier | 2tc(SYSCLK) + tw(IQSW) | cycles | |||
tw(STROBH) | QEP Strobe High time | Asynchronous(2)/Synchronous | 2tc(SYSCLK) | cycles | |
With input qualifier | 2tc(SYSCLK) + tw(IQSW) | cycles | |||
tw(STROBL) | QEP Strobe Input Low time | Asynchronous(2)/Synchronous | 2tc(SYSCLK) | cycles | |
With input qualifier | 2tc(SYSCLK) + tw(IQSW) | cycles |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
td(CNTR)xin | Delay time, external clock to counter increment | 4tc(SYSCLK) | cycles | |
td(PCS-OUT)QEP | Delay time, QEP input edge to position compare sync output | 6tc(SYSCLK) | cycles |
The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a dedicated calibration delay line. For each ePWM module, there are two HR outputs:
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
NOTE
The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.
Table 4-63 lists the high-resolution PWM switching characteristics.
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Micro Edge Positioning (MEP) step size(1) | 150 | 310 | ps |
The SDFM is a four-channel digital filter designed specifically for current measurement and resolver position decoding in motor control applications. Each channel can receive an independent sigma-delta (ΣΔ) modulated bit stream. The bit streams are processed by four individually programmable digital decimation filters. The filter set includes a fast comparator for immediate digital threshold comparisons for overcurrent and undercurrent monitoring. Figure 4-54 shows a block diagram of the SDFMs.
SDFM features include:
Table 4-64 shows the SDFM timing requirements. Figure 4-55 through Figure 4-58 show the SDFM timing diagrams.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Mode 0 | ||||
tc(SDC)M0 | Cycle time, SDx_Cy | 40 | 256 * SYSCLK period | ns |
tw(SDCH)M0 | Pulse duration, SDx_Cy high | 10 | tc(SDC)M0 – 10 | ns |
tsu(SDDV-SDCH)M0 | Setup time, SDx_Dy valid before SDx_Cy goes high | 5 | ns | |
th(SDCH-SDD)M0 | Hold time, SDx_Dy wait after SDx_Cy goes high | 5 | ns | |
Mode 1 | ||||
tc(SDC)M1 | Cycle time, SDx_Cy | 80 | 256 * SYSCLK period | ns |
tw(SDCH)M1 | Pulse duration, SDx_Cy high | 10 | tc(SDC)M1 – 10 | ns |
tsu(SDDV-SDCL)M1 | Setup time, SDx_Dy valid before SDx_Cy goes low | 5 | ns | |
tsu(SDDV-SDCH)M1 | Setup time, SDx_Dy valid before SDx_Cy goes high | 5 | ns | |
th(SDCL-SDD)M1 | Hold time, SDx_Dy wait after SDx_Cy goes low | 5 | ns | |
th(SDCH-SDD)M1 | Hold time, SDx_Dy wait after SDx_Cy goes high | 5 | ns | |
Mode 2 | ||||
tc(SDD)M2 | Cycle time, SDx_Dy | 8 * tc(SYSCLK) | 20 * tc(SYSCLK) | ns |
tw(SDDH)M2 | Pulse duration, SDx_Dy high | 10 | ns | |
Mode 3 | ||||
tc(SDC)M3 | Cycle time, SDx_Cy | 40 | 256 * SYSCLK period | ns |
tw(SDCH)M3 | Pulse duration, SDx_Cy high | 10 | tc(SDC)M3 – 5 | ns |
tsu(SDDV-SDCH)M3 | Setup time, SDx_Dy valid before SDx_Cy goes high | 5 | ns | |
th(SDCH-SDD)M3 | Hold time, SDx_Dy wait after SDx_Cy goes high | 5 | ns |
NOTE
The CAN module uses the IP known as D_CAN. This document uses the names CAN and D_CAN interchangeably to reference this peripheral.
The CAN module implements the following features:
NOTE
For a CANx Bit-CLK of 200 MHz, the smallest bit rate possible is 7.8125 kbps.
NOTE
The accuracy of the on-chip zero-pin oscillator is in Table 4-18, Internal Oscillator Electrical Characteristics. Depending on parameters such as the CAN bit timing settings, bit rate, bus length, and propagation delay, the accuracy of this oscillator may not meet the requirements of the CAN protocol. In this situation, an external clock source must be used.
The I2C module has the following features:
Figure 4-59 shows how the I2C peripheral module interfaces within the device.
Table 4-65 shows the I2C timing requirements. Table 4-66 shows the I2C switching characteristics.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
th(SDA-SCL)START | Hold time, START condition, SCL fall delay after SDA fall | 0.6 | µs | ||
tsu(SCL-SDA)START | Setup time, Repeated START, SCL rise before SDA fall delay | 0.6 | µs | ||
th(SCL-DAT) | Hold time, data after SCL fall | 0 | µs | ||
tsu(DAT-SCL) | Setup time, data before SCL rise | 100 | ns | ||
tr(SDA) | Rise time, SDA | Input tolerance | 20 | 300 | ns |
tr(SCL) | Rise time, SCL | Input tolerance | 20 | 300 | ns |
tf(SDA) | Fall time, SDA | Input tolerance | 11.4 | 300 | ns |
tf(SCL) | Fall time, SCL | Input tolerance | 11.4 | 300 | ns |
tsu(SCL-SDA)STOP | Setup time, STOP condition, SCL rise before SDA rise delay | 0.6 | µs |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fSCL | SCL clock frequency | 0 | 400 | kHz | |
tw(SCLL) | Pulse duration, SCL clock low | 1.3 | µs | ||
tw(SCLH) | Pulse duration, SCL clock high | 0.6 | µs | ||
tw(SP) | Pulse duration of spikes that will be suppressed by the input filter | 0 | 50 | ns | |
tBUF | Bus free time between STOP and START conditions | 1.3 | µs | ||
tv(SCL-DAT) | Valid time, data after SCL fall | 0.9 | µs | ||
tv(SCL-ACK) | Valid time, Acknowledge after SCL fall | 0.9 | µs | ||
VIL | Valid low-level input voltage | –0.3 | 0.3 * VDDIO | V | |
VIH | Valid high-level input voltage | 0.7 * VDDIO | VDDIO + 0.3 | V | |
VOL | Low-level output voltage | Sinking 3 mA | 0 | 0.4 | V |
II | Input current on pins | 0.1 Vbus < Vi < 0.9 Vbus | –10 | 10 | µA |
NOTE
To meet all of the I2C protocol timing specifications, the I2C module clock must be configured between 7 MHz to 12 MHz.
The McBSP module has the following features:
where CLKSRG source could be LSPCLK, CLKX, or CLKR.
Figure 4-60 shows the block diagram of the McBSP module.
Table 4-67 shows the McBSP timing requirements. Table 4-68 shows the McBSP switching characteristics. Figure 4-61 and Figure 4-62 show the McBSP timing diagrams.
NO. | MIN | MAX | UNIT | |||
---|---|---|---|---|---|---|
McBSP module clock (CLKG, CLKX, CLKR) range | 1 | kHz | ||||
25 | MHz | |||||
McBSP module cycle time (CLKG, CLKX, CLKR) range | 40 | ns | ||||
1 | ms | |||||
M11 | tc(CKRX) | Cycle time, CLKR/X | CLKR/X ext | 2P | ns | |
M12 | tw(CKRX) | Pulse duration, CLKR/X high or CLKR/X low | CLKR/X ext | P – 7 | ns | |
M13 | tr(CKRX) | Rise time, CLKR/X | CLKR/X ext | 7 | ns | |
M14 | tf(CKRX) | Fall time, CLKR/X | CLKR/X ext | 7 | ns | |
M15 | tsu(FRH-CKRL) | Setup time, external FSR high before CLKR low | CLKR int | 18 | ns | |
CLKR ext | 2 | |||||
M16 | th(CKRL-FRH) | Hold time, external FSR high after CLKR low | CLKR int | 0 | ns | |
CLKR ext | 6 | |||||
M17 | tsu(DRV-CKRL) | Setup time, DR valid before CLKR low | CLKR int | 18 | ns | |
CLKR ext | 5 | |||||
M18 | th(CKRL-DRV) | Hold time, DR valid after CLKR low | CLKR int | 0 | ns | |
CLKR ext | 3 | |||||
M19 | tsu(FXH-CKXL) | Setup time, external FSX high before CLKX low | CLKX int | 18 | ns | |
CLKX ext | 2 | |||||
M20 | th(CKXL-FXH) | Hold time, external FSX high after CLKX low | CLKX int | 0 | ns | |
CLKX ext | 6 |
NO. | PARAMETER | MIN | MAX | UNIT | |||
---|---|---|---|---|---|---|---|
M1 | tc(CKRX) | Cycle time, CLKR/X | CLKR/X int | 2P | ns | ||
M2 | tw(CKRXH) | Pulse duration, CLKR/X high | CLKR/X int | D – 5 (3) | D + 5 (3) | ns | |
M3 | tw(CKRXL) | Pulse duration, CLKR/X low | CLKR/X int | C – 5 (3) | C + 5 (3) | ns | |
M4 | td(CKRH-FRV) | Delay time, CLKR high to internal FSR valid | CLKR int | 0 | 4 | ns | |
CLKR ext | 3 | 27 | |||||
M5 | td(CKXH-FXV) | Delay time, CLKX high to internal FSX valid | CLKX int | 0 | 4 | ns | |
CLKX ext | 3 | 27 | |||||
M6 | tdis(CKXH-DXHZ) | Disable time, CLKX high to DX high impedance following last data bit | CLKX int | 8 | ns | ||
CLKX ext | 14 | ||||||
M7 | td(CKXH-DXV) | Delay time, CLKX high to DX valid. | CLKX int | 9 | ns | ||
This applies to all bits except the first bit transmitted. | CLKX ext | 28 | |||||
Delay time, CLKX high to DX valid | DXENA = 0 | CLKX int | 8 | ||||
CLKX ext | 14 | ||||||
Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes | DXENA = 1 | CLKX int | P + 8 | ||||
CLKX ext | P + 14 | ||||||
M8 | ten(CKXH-DX) | Enable time, CLKX high to DX driven | DXENA = 0 | CLKX int | 0 | ns | |
CLKX ext | 6 | ||||||
Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes | DXENA = 1 | CLKX int | P | ||||
CLKX ext | P + 6 | ||||||
M9 | td(FXH-DXV) | Delay time, FSX high to DX valid | DXENA = 0 | FSX int | 8 | ns | |
FSX ext | 14 | ||||||
Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. | DXENA = 1 | FSX int | P + 8 | ||||
FSX ext | P + 14 | ||||||
M10 | ten(FXH-DX) | Enable time, FSX high to DX driven | DXENA = 0 | FSX int | 0 | ns | |
FSX ext | 6 | ||||||
Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode | DXENA = 1 | FSX int | P | ||||
FSX ext | P + 6 |
For CLKSTP = 10b and CLKXP = 0, Table 4-69 shows the timing requirements, Table 4-70 shows the switching characteristics, and Figure 4-63 shows the timing diagram.
NO. | MASTER | SLAVE | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
M30 | tsu(DRV-CKXL) | Setup time, DR valid before CLKX low | 30 | 8P – 10 | ns | ||
M31 | th(CKXL-DRV) | Hold time, DR valid after CLKX low | 1 | 8P – 10 | ns | ||
M32 | tsu(BFXL-CKXH) | Setup time, FSX low before CLKX high | 8P + 10 | ns | |||
M33 | tc(CKX) | Cycle time, CLKX | 2P(2) | 16P | ns |
NO. | PARAMETER | MASTER | SLAVE | UNIT | |||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
M24 | th(CKXL-FXL) | Hold time, FSX low after CLKX low | 2P(1) | ns | |||
M25 | td(FXL-CKXH) | Delay time, FSX low to CLKX high | P | ns | |||
M28 | tdis(FXH-DXHZ) | Disable time, DX high impedance following last data bit from FSX high | 6 | 6P + 6 | ns | ||
M29 | td(FXL-DXV) | Delay time, FSX low to DX valid | 6 | 4P + 6 | ns |
For CLKSTP = 11b and CLKXP = 0, Table 4-71 shows the timing requirements, Table 4-72 shows the switching characteristics, and Figure 4-64 shows the timing diagram.
NO. | MASTER | SLAVE | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
M39 | tsu(DRV-CKXH) | Setup time, DR valid before CLKX high | 30 | 8P – 10 | ns | ||
M40 | th(CKXH-DRV) | Hold time, DR valid after CLKX high | 1 | 8P – 10 | ns | ||
M41 | tsu(FXL-CKXH) | Setup time, FSX low before CLKX high | 16P + 10 | ns | |||
M42 | tc(CKX) | Cycle time, CLKX | 2P(2) | 16P | ns |
NO. | PARAMETER | MASTER | SLAVE | UNIT | |||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
M34 | th(CKXL-FXL) | Hold time, FSX low after CLKX low | P | ns | |||
M35 | td(FXL-CKXH) | Delay time, FSX low to CLKX high | 2P(1) | ns | |||
M37 | tdis(CKXL-DXHZ) | Disable time, DX high impedance following last data bit from CLKX low | P + 6 | 7P + 6 | ns | ||
M38 | td(FXL-DXV) | Delay time, FSX low to DX valid | 6 | 4P + 6 | ns |
For CLKSTP = 10b and CLKXP = 1, Table 4-73 shows the timing requirements, Table 4-74 shows the switching characteristics, and Figure 4-65 shows the timing diagram.
NO. | MASTER | SLAVE | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
M49 | tsu(DRV-CKXH) | Setup time, DR valid before CLKX high | 30 | 8P – 10 | ns | ||
M50 | th(CKXH-DRV) | Hold time, DR valid after CLKX high | 1 | 8P – 10 | ns | ||
M51 | tsu(FXL-CKXL) | Setup time, FSX low before CLKX low | 8P + 10 | ns | |||
M52 | tc(CKX) | Cycle time, CLKX | 2P(2) | 16P | ns |
NO. | PARAMETER | MASTER | SLAVE | UNIT | |||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
M43 | th(CKXH-FXL) | Hold time, FSX low after CLKX high | 2P(1) | ns | |||
M44 | td(FXL-CKXL) | Delay time, FSX low to CLKX low | P | ns | |||
M47 | tdis(FXH-DXHZ) | Disable time, DX high impedance following last data bit from FSX high | 6 | 6P + 6 | ns | ||
M48 | td(FXL-DXV) | Delay time, FSX low to DX valid | 6 | 4P + 6 | ns |
For CLKSTP = 11b and CLKXP = 1, Table 4-75 shows the timing requirements, Table 4-76 shows the switching characteristics, and Figure 4-66 shows the timing diagram.
NO. | MASTER | SLAVE | UNIT | ||||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
M58 | tsu(DRV-CKXL) | Setup time, DR valid before CLKX low | 30 | 8P – 10 | ns | ||
M59 | th(CKXL-DRV) | Hold time, DR valid after CLKX low | 1 | 8P – 10 | ns | ||
M60 | tsu(FXL-CKXL) | Setup time, FSX low before CLKX low | 16P + 10 | ns | |||
M61 | tc(CKX) | Cycle time, CLKX | 2P(2) | 16P | ns |
NO. | PARAMETER | MASTER(2) | SLAVE | UNIT | |||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
M53 | th(CKXH-FXL) | Hold time, FSX low after CLKX high | P | ns | |||
M54 | td(FXL-CKXL) | Delay time, FSX low to CLKX low | 2P(1) | ns | |||
M55 | td(CLKXH-DXV) | Delay time, CLKX high to DX valid | –2 | 0 | 3P + 6 | 5P + 20 | ns |
M56 | tdis(CKXH-DXHZ) | Disable time, DX high impedance following last data bit from CLKX high | P + 6 | 7P + 6 | ns | ||
M57 | td(FXL-DXV) | Delay time, FSX low to DX valid | 6 | 4P + 6 | ns |
The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit baud-select register. Figure 4-67 shows the SCI block diagram.
Features of the SCI module include:
NOTE: Both pins can be used as GPIO if not used for SCI.
NOTE
All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no effect.
The major elements used in full-duplex operation include:
The SCI receiver and transmitter operate independently.
The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications between the microcontroller and external peripherals or another controller. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The port supports 16-level receive and transmit FIFOs for reducing CPU servicing overhead.
The SPI module features include:
The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is transmitted and received a half-cycle before the SPICLK transition. As a result, both controllers send and receive data simultaneously. The application software determines whether the data is meaningful or dummy data. There are three possible methods for data transmission:
The master can initiate a data transfer at any time because it controls the SPICLK signal. The software, however, determines how the master detects when the slave is ready to broadcast data.
Figure 4-68 shows the SPI CPU Interface.
The following sections contain the SPI External Timings in Non-High-Speed Mode:
Section 4.10.5.1.1 | Non-High-Speed Master Mode Timings |
Section 4.10.5.1.2 | Non-High-Speed Slave Mode Timings |
The following sections contain the SPI External Timings in High-Speed Mode:
Section 4.10.5.1.3 | High-Speed Master Mode Timings |
Section 4.10.5.1.4 | High-Speed Slave Mode Timings |
NOTE
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK, SPISIMO, and SPISOMI.
For more information about the SPI in High-Speed mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
To use the SPI in High-Speed mode, the application must use the high-speed enabled GPIOs (see Section 3.4.5).
Table 4-77 lists the SPI master mode switching characteristics where the clock phase = 0. Figure 4-69 shows the SPI master mode external timing where the clock phase = 0.
Table 4-78 lists the SPI master mode switching characteristics where the clock phase = 1. Figure 4-70 shows the SPI master mode external timing where the clock phase = 1.
Table 4-79 lists the SPI master mode timing requirements.
NO. | PARAMETER | (BRR + 1) CONDITION(1) | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | tc(SPC)M | Cycle time, SPICLK | Even | 4tc(LSPCLK) | 128tc(LSPCLK) | ns |
Odd | 5tc(LSPCLK) | 127tc(LSPCLK) | ||||
2 | tw(SPC1)M | Pulse duration, SPICLK, first pulse | Even | 0.5tc(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns |
Odd | 0.5tc(SPC)M + 0.5tc(LSPCLK) – 3 |
0.5tc(SPC)M + 0.5tc(LSPCLK) + 3 |
||||
3 | tw(SPC2)M | Pulse duration, SPICLK, second pulse | Even | 0.5tc(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3 |
0.5tc(SPC)M – 0.5tc(LSPCLK) + 3 |
||||
4 | td(SIMO)M | Delay time, SPICLK to SPISIMO valid | Even, Odd | 3 | ns | |
5 | tv(SIMO)M | Valid time, SPISIMO valid after SPICLK | Even | 0.5tc(SPC)M – 3 | ns | |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3 |
|||||
23 | td(SPC)M | Delay time, SPISTE active to SPICLK | Even | tc(SPC)M – 3 | ns | |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3 |
|||||
24 | td(STE)M | Delay time, SPICLK to SPISTE inactive | Even | 0.5tc(SPC)M – 3 | ns | |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3 |
NO. | PARAMETER | (BRR + 1) CONDITION(1) | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | tc(SPC)M | Cycle time, SPICLK | Even | 4tc(LSPCLK) | 128tc(LSPCLK) | ns |
Odd | 5tc(LSPCLK) | 127tc(LSPCLK) | ||||
2 | tw(SPC1)M | Pulse duration, SPICLK, first pulse | Even | 0.5tc(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3 |
0.5tc(SPC)M – 0.5tc(LSPCLK) + 3 |
||||
3 | tw(SPC2)M | Pulse duration, SPICLK, second pulse | Even | 0.5tc(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns |
Odd | 0.5tc(SPC)M + 0.5tc(LSPCLK) – 3 |
0.5tc(SPC)M + 0.5tc(LSPCLK) + 3 |
||||
4 | td(SIMO)M | Delay time, SPISIMO valid to SPICLK | Even | 0.5tc(SPC)M – 3 | ns | |
Odd | 0.5tc(SPC)M + 0.5tc(LSPCLK) – 3 |
|||||
5 | tv(SIMO)M | Valid time, SPISIMO valid after SPICLK | Even | 0.5tc(SPC)M – 3 | ns | |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3 |
|||||
23 | td(SPC)M | Delay time, SPISTE active to SPICLK | Even, Odd | tc(SPC)M – 3 | ns | |
24 | td(STE)M | Delay time, SPICLK to SPISTE inactive | Even | 0.5tc(SPC)M – 3 | ns | |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3 |
NO. | (BRR + 1) CONDITION(1) | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
8 | tsu(SOMI)M | Setup time, SPISOMI valid before SPICLK | Even, Odd | 20 | ns | |
9 | th(SOMI)M | Hold time, SPISOMI valid after SPICLK | Even, Odd | 0 | ns |
Table 4-80 lists the SPI slave mode switching characteristics. Table 4-81 lists the SPI slave mode timing requirements.
Figure 4-71 shows the SPI slave mode external timing where the clock phase = 0. Figure 4-72 shows the SPI slave mode external timing where the clock phase = 1.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
15 | td(SOMI)S | Delay time, SPICLK to SPISOMI valid | 20 | ns | |
16 | tv(SOMI)S | Valid time, SPISOMI valid after SPICLK | 0 | ns |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
12 | tc(SPC)S | Cycle time, SPICLK | 4tc(SYSCLK) | ns | |
13 | tw(SPC1)S | Pulse duration, SPICLK, first pulse | 2tc(SYSCLK) – 1 | ns | |
14 | tw(SPC2)S | Pulse duration, SPICLK, second pulse | 2tc(SYSCLK) – 1 | ns | |
19 | tsu(SIMO)S | Setup time, SPISIMO valid before SPICLK | 1.5tc(SYSCLK) | ns | |
20 | th(SIMO)S | Hold time, SPISIMO valid after SPICLK | 1.5tc(SYSCLK) | ns | |
25 | tsu(STE)S | Setup time, SPISTE active before SPICLK | 1.5tc(SYSCLK) | ns | |
26 | th(STE)S | Hold time, SPISTE inactive after SPICLK | 1.5tc(SYSCLK) | ns |
Table 4-82 lists the SPI high-speed master mode switching characteristics where the clock phase = 0. Figure 4-73 shows the high-speed SPI master mode external timing where the clock phase = 0.
Table 4-83 lists the SPI high-speed master mode switching characteristics where the clock phase = 1. Figure 4-74 shows the high-speed SPI master mode external timing where the clock phase = 1.
Table 4-84 lists the SPI high-speed master mode timing requirements.
NO. | PARAMETER | (BRR + 1) CONDITION(1) | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | tc(SPC)M | Cycle time, SPICLK | Even | 4tc(LSPCLK) | 128tc(LSPCLK) | ns |
Odd | 5tc(LSPCLK) | 127tc(LSPCLK) | ||||
2 | tw(SPC1)M | Pulse duration, SPICLK, first pulse | Even | 0.5tc(SPC)M – 1 | 0.5tc(SPC)M + 1 | ns |
Odd | 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 |
0.5tc(SPC)M + 0.5tc(LSPCLK) + 1 |
||||
3 | tw(SPC2)M | Pulse duration, SPICLK, second pulse | Even | 0.5tc(SPC)M – 1 | 0.5tc(SPC)M + 1 | ns |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 |
0.5tc(SPC)M – 0.5tc(LSPCLK) + 1 |
||||
4 | td(SIMO)M | Delay time, SPICLK to SPISIMO valid | Even, Odd | 1 | ns | |
5 | tv(SIMO)M | Valid time, SPISIMO valid after SPICLK | Even | 0.5tc(SPC)M – 1 | ns | |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 |
|||||
23 | td(SPC)M | Delay time, SPISTE active to SPICLK | Even | tc(SPC)M – 1 | ns | |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 |
|||||
24 | td(STE)M | Delay time, SPICLK to SPISTE inactive | Even | 0.5tc(SPC)M – 1 | ns | |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 |
NO. | PARAMETER | (BRR + 1) CONDITION(1) | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | tc(SPC)M | Cycle time, SPICLK | Even | 4tc(LSPCLK) | 128tc(LSPCLK) | ns |
Odd | 5tc(LSPCLK) | 127tc(LSPCLK) | ||||
2 | tw(SPC1)M | Pulse duration, SPICLK, first pulse | Even | 0.5tc(SPC)M – 1 | 0.5tc(SPC)M + 1 | ns |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 |
0.5tc(SPC)M – 0.5tc(LSPCLK) + 1 |
||||
3 | tw(SPC2)M | Pulse duration, SPICLK, second pulse | Even | 0.5tc(SPC)M – 1 | 0.5tc(SPC)M + 1 | ns |
Odd | 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 |
0.5tc(SPC)M + 0.5tc(LSPCLK) + 1 |
||||
4 | td(SIMO)M | Delay time, SPISIMO valid to SPICLK | Even | 0.5tc(SPC)M – 1 | ns | |
Odd | 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 |
|||||
5 | tv(SIMO)M | Valid time, SPISIMO valid after SPICLK | Even | 0.5tc(SPC)M – 1 | ns | |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 |
|||||
23 | td(SPC)M | Delay time, SPISTE active to SPICLK | Even, Odd | tc(SPC)M – 1 | ns | |
24 | td(STE)M | Delay time, SPICLK to SPISTE inactive | Even | 0.5tc(SPC)M – 1 | ns | |
Odd | 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 |
NO. | (BRR + 1) CONDITION(1) | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
8 | tsu(SOMI)M | Setup time, SPISOMI valid before SPICLK | Even, Odd | 1 | ns | |
9 | th(SOMI)M | Hold time, SPISOMI valid after SPICLK | Even, Odd | 5 | ns |
Table 4-85 lists the SPI high-speed slave mode switching characteristics. Table 4-86 lists the SPI high-speed slave mode timing requirements.
Figure 4-75 shows the high-speed SPI slave mode external timing where the clock phase = 0. Figure 4-76 shows the high-speed SPI slave mode external timing where the clock phase = 1.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
15 | td(SOMI)S | Delay time, SPICLK to SPISOMI valid | 9 | ns | |
16 | tv(SOMI)S | Valid time, SPISOMI valid after SPICLK | 0 | ns |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
12 | tc(SPC)S | Cycle time, SPICLK | 4tc(SYSCLK) | ns | |
13 | tw(SPC1)S | Pulse duration, SPICLK, first pulse | 2tc(SYSCLK) – 1 | ns | |
14 | tw(SPC2)S | Pulse duration, SPICLK, second pulse | 2tc(SYSCLK) – 1 | ns | |
19 | tsu(SIMO)S | Setup time, SPISIMO valid before SPICLK | 1.5tc(SYSCLK) | ns | |
20 | th(SIMO)S | Hold time, SPISIMO valid after SPICLK | 1.5tc(SYSCLK) | ns | |
25 | tsu(STE)S | Setup time, SPISTE active before SPICLK | 1.5tc(SYSCLK) | ns | |
26 | th(STE)S | Hold time, SPISTE inactive after SPICLK | 1.5tc(SYSCLK) | ns |
The USB controller operates as a full-speed or low-speed function controller during point-to-point communications with USB host or device functions.
The USB module has the following features:
Figure 4-77 shows the USB block diagram.
NOTE
The accuracy of the on-chip zero-pin oscillator (Table 4-18, Internal Oscillator Electrical Characteristics) will not meet the accuracy requirements of the USB protocol. An external clock source must be used for applications using USB. For applications using the USB boot mode, see Section 5.10 (Boot ROM and Peripheral Booting) for clock frequency requirements.
Table 4-87 shows the USB input ports DP and DM timing requirements. Table 4-88 shows the USB output ports DP and DM switching characteristics.
MIN | MAX | UNIT | ||
---|---|---|---|---|
V(CM) | Differential input common mode range | 0.8 | 2.5 | V |
Z(IN) | Input impedance | 300 | kΩ | |
VCRS | Crossover voltage | 1.3 | 2.0 | V |
VIL | Static SE input logic-low level | 0.8 | V | |
VIH | Static SE input logic-high level | 2.0 | V | |
VDI | Differential input voltage | 0.2 | V |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
VOH | D+, D– single-ended | USB 2.0 load conditions | 2.8 | 3.6 | V |
VOL | D+, D– single-ended | USB 2.0 load conditions | 0 | 0.3 | V |
Z(DRV) | D+, D– impedance | 28 | 44 | Ω | |
tr | Rise time | Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ |
4 | 20 | ns |
tf | Fall time | Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ |
4 | 20 | ns |
The uPP interface is a high-speed parallel interface with dedicated data lines and minimal control signals. The uPP interface is designed to interface cleanly with high-speed ADCs or DACs with 8-bit data width. It can also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital data transfer. It can operate in receive mode or transmit mode (simplex mode).
The uPP interface includes an internal DMA controller to maximize throughput and minimize CPU overhead during high-speed data transmission. All uPP transactions use internal DMA to feed data to or retrieve data from the I/O channels. Even though there is only one I/O channel, the DMA controller includes two DMA channels to support data interleave mode, in which all DMA resources service a single I/O channel.
On this device, the uPP interface is the dedicated resource for the CPU1 subsystem. CPU1, CPU1.CLA1, and CPU1.DMA have access to this module. Two dedicated 512-byte data RAMs (also known as MSG RAMs) are tightly coupled with the uPP module (one for each, TX and RX). These data RAMs are used to store the bulk of data to avoid frequent interruptions to the CPU. Only CPU1 and CPU1.CLA1 have access to these data RAMs. Figure 4-78 shows the integration of the uPP on this device.
NOTE
On some TI devices, the uPP module is also called the Radio Peripheral Interface (RPI) module.
The uPP interface supports the following:
Figure 4-79 shows the uPP functional block diagram.
Table 4-89 shows the uPP timing requirements. Table 4-90 shows the uPP switching characteristics. Figure 4-80 through Figure 4-83 show the uPP timing diagrams.
NO. | MIN | MAX | UNIT | |||
---|---|---|---|---|---|---|
1 | tc(CLK) | Cycle time, CLK | SDR mode | 20 | ns | |
DDR mode | 40 | |||||
2 | tw(CLKH) | Pulse width, CLK high | SDR mode | 8 | ns | |
DDR mode | 18 | |||||
3 | tw(CLKL) | Pulse width, CLK low | SDR mode | 8 | ns | |
DDR mode | 18 | |||||
4 | tsu(STV-CLKH) | Setup time, START valid before CLK high | 4 | ns | ||
5 | th(CLKH-STV) | Hold time, START valid after CLK high | 0.8 | ns | ||
6 | tsu(ENV-CLKH) | Setup time, ENABLE valid before CLK high | 4 | ns | ||
7 | th(CLKH-ENV) | Hold time, ENABLE valid after CLK high | 0.8 | ns | ||
8 | tsu(DV-CLKH) | Setup time, DATA valid before CLK high | 4 | ns | ||
9 | th(CLKH-DV) | Hold time, DATA valid after CLK high | 0.8 | ns | ||
10 | tsu(DV-CLKL) | Setup time, DATA valid before CLK low | 4 | ns | ||
11 | th(CLKL-DV) | Hold time, DATA valid after CLK low | 0.8 | ns | ||
19 | tsu(WTV-CLKH) | Setup time, WAIT valid before CLK high | SDR mode | 20 | ns | |
20 | th(CLKH-WTV) | Hold time, WAIT valid after CLK high | SDR mode | 0 | ns | |
21 | tsu(WTV-CLKL) | Setup time, WAIT valid before CLK low | DDR mode | 20 | ns | |
22 | th(CLKL-WTV) | Hold time, WAIT valid after CLK low | DDR mode | 0 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
12 | tc(CLK) | Cycle time, CLK | SDR mode | 20 | ns | |
DDR mode | 40 | |||||
13 | tw(CLKH) | Pulse width, CLK high | SDR mode | 8 | ns | |
DDR mode | 18 | |||||
14 | tw(CLKL) | Pulse width, CLK low | SDR mode | 8 | ns | |
DDR mode | 18 | |||||
15 | td(CLKH-STV) | Delay time, START valid after CLK high | 3 | 12 | ns | |
16 | td(CLKH-ENV) | Delay time, ENABLE valid after CLK high | 3 | 12 | ns | |
17 | td(CLKH-DV) | Delay time, DATA valid after CLK high | 3 | 12 | ns | |
18 | td(CLKL-DV) | Delay time, DATA valid after CLK low | 3 | 12 | ns |