• Menu
  • Product
  • Email
  • PDF
  • Order now

  • TPA3110D2-Q1 15-W Filter-Free Stereo Class-D Audio Power Amplifier With SpeakerGuard™

    • SLOS794B September   2012  – September 2015 TPA3110D2-Q1

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • TPA3110D2-Q1 15-W Filter-Free Stereo Class-D Audio Power Amplifier With SpeakerGuard™
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Characteristics
    6. 6.6 DC Characteristics
    7. 6.7 AC Characteristics
    8. 6.8 AC Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DC Detect
      2. 7.3.2 Short-Circuit Protection and Automatic Recovery Feature
      3. 7.3.3 Thermal Protection
      4. 7.3.4 GVDD Supply
    4. 7.4 Device Functional Modes
      1. 7.4.1 PBTL Select
      2. 7.4.2 Gain Setting Through GAIN0 and GAIN1 Inputs
      3. 7.4.3 SD Operation
      4. 7.4.4 PLIMIT
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 TPA3110D2-Q1 Modulation Scheme
        2. 8.2.2.2 Ferrite Bead Filter Considerations
        3. 8.2.2.3 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
        4. 8.2.2.4 When to Use an Output Filter for EMI Suppression
        5. 8.2.2.5 Input Resistance
        6. 8.2.2.6 Input Capacitor, CI
        7. 8.2.2.7 BSN and BSP Capacitors
        8. 8.2.2.8 Differential Inputs
        9. 8.2.2.9 Using Low-ESR Capacitors
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • PWP|28
    • MPDS373B
Thermal pad, mechanical data (Package|Pins)
  • PWP|28
    • PPTD156P
Orderable Information
  • slos794b_oa
  • slos794b_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

TPA3110D2-Q1 15-W Filter-Free Stereo Class-D Audio Power Amplifier With SpeakerGuard™

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C2
  • 15-W/ch Into 8-Ω Loads at 10% THD+N From a 16-V Supply
  • 10-W/ch Into 8-Ω Loads at 10% THD+N From a 13-V Supply
  • 30-W Into a 4-Ω Mono Load at 10% THD+N From a 16-V Supply
  • 90% Efficient Class-D Operation Eliminates Need for Heat Sinks
  • Wide Supply Voltage Range Allows Operation from 8 V to 26 V
  • Filter-Free Operation
  • SpeakerGuard™ Protection Circuitry Includes Adjustable Power Limiter Plus DC Protection
  • Flow Through Pin Out Facilitates Easy Board Layout
  • Robust Pin-to-Pin Short-Circuit Protection and Thermal Protection with Auto Recovery Option
  • Excellent THD+N and Pop-Free Performance
  • Four Selectable Fixed Gain Settings
  • Differential Inputs

2 Applications

  • Automotive Noise Generation for HEV/EV
  • Automotive Emergency Call Systems (eCall)
  • Automotive Infotainment Systems (i.e. Head Unit, Connectivity Gateway, Cluster, Telematics, Navigation)
  • ADAS Noise Generation for Blind Spot Detection, Security and Alarm Systems
  • Professional Audio Equipment (Performance Amplifiers, Premium Microphones)
  • Aerospace and Aviation Audio Systems

3 Description

The TPA3110D2-Q1 is a 15-W (per channel) efficient, Class-D audio power amplifier for driving bridged-tied stereo speakers. Advanced EMI suppression technology enables the use of inexpensive ferrite bead filters at the outputs while meeting EMC requirements. SpeakerGuard protection circuitry includes an adjustable power limiter and a DC detection circuit. The adjustable power limiter allows the user to set a virtual voltage rail lower than the chip supply to limit the amount of current through the speaker. The DC detect circuit measures the frequency and amplitude of the PWM signal and shuts off the output stage if the input capacitors are damaged or shorts exist on the inputs.

The TPA3110D2-Q1 can drive stereo speakers as low as 4 Ω. The high efficiency of the device, 90%, eliminates the need for an external heat sink when playing music.

The outputs are also fully protected against shorts to GND, VCC, and output-to-output. The short-circuit protection and thermal protection includes an auto-recovery feature.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPA3110D2-Q1 HTSSOP (28) 9.70 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

TPA3110D2-Q1 Simplified Application Schematic

TPA3110D2-Q1 sim_app_cir_los528.gif

4 Revision History

Changes from A Revision (December 2012) to B Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo

Changes from * Revision (September, 2012) to A Revision

  • Changed TA from 25°C to –40°C to 125°C in DC and AC Characteristics tables.Go

5 Pin Configuration and Functions

PWP Package
28-Pin HTSSOP With PowerPAD™ IC Package
Top View
TPA3110D2-Q1 PinOut_los528.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 SD I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled), TTL logic levels with compliance to AVCC.
2 FAULT O Open drain output used to display short circuit or DC detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both short circuit faults and DC detect faults must be reset by cycling PVCC.
3 LINP I Positive audio input for left channel, biased at 3 V.
4 LINN I Negative audio input for left channel, biased at 3 V.
5 GAIN0 I Gain select least significant bit, TTL logic levels with compliance to AVCC.
6 GAIN1 I Gain select most significant bit, TTL logic levels with compliance to AVCC.
7 AVCC P Analog supply
8 AGND — Analog signal ground, connect to the thermal pad.
9 GVDD O High-side FET gate drive supply. The nominal voltage is 7 V. GVDD should also be used as a supply for the PLIMIT function.
10 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit.
11 RINN I Negative audio input for right channel, biased at 3 V.
12 RINP I Positive audio input for right channel, biased at 3 V.
13 NC — Not connected
14 PBTL I Parallel BTL mode switch
15 PVCCR P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally.
16 PVCCR P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally.
17 BSPR I Bootstrap I/O for right channel, positive high-side FET
18 OUTPR O Class-D H-bridge positive output for right channel
19 PGND — Power ground for the H-bridges
20 OUTNR O Class-D H-bridge negative output for right channel
21 BSNR I Bootstrap I/O for right channel, negative high-side FET
22 BSNL I Bootstrap I/O for left channel, negative high-side FET
23 OUTNL O Class-D H-bridge negative output for left channel
24 PGND — Power ground for the H-bridges
25 OUTPL O Class-D H-bridge positive output for left channel
26 BSPL I Bootstrap I/O for left channel, positive high-side FET
27 PVCCL P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally.
28 PVCCL P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage AVCC, PVCC –0.3 30 V
VI Interface pin voltage SD, GAIN0, GAIN1, PBTL, FAULT(2) –0.3 VCC + 0.3 V
< 10 V/ms
PLIMIT –0.3 GVDD + 0.3 V
RINN, RINP, LINN, LINP –0.3 6.3 V
RL Minimum load resistance BTL: PVCC > 15 V 4.8
BTL: PVCC ≤ 15 V 3.2
PBTL 3.2
Continuous total power dissipation See the Thermal Information Table
TA Operating free-air temperature –40 125 °C
TJ Operating junction temperature(3) –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-kΩ resistor in series with the pins, per application note SLUA626.
(3) The TPA3110D2-Q1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Brief SLMA002 for more information about using the TSSOP thermal pad.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V
Charged-device model (CDM), per AEC Q100-011 ±250
Machine Model (MM) per JESD22-A115 ±200
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage PVCC, AVCC 8 26 V
VIH High-level input voltage SD, GAIN0, GAIN1, PBTL 2 V
VIL Low-level input voltage SD, GAIN0, GAIN1, PBTL 0.8 V
VOL Low-level output voltage FAULT, RPULL-UP = 100k, VCC = 26 V 0.8 V
IIH High-level input current SD, GAIN0, GAIN1, PBTL, VI = 2 V, VCC = 18 V 50 µA
IIL Low-level input current SD, GAIN0, GAIN1, PBTL, VI = 0.8 V, VCC = 18 V 5 µA
TA Operating free-air temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1)(2) TPA3110D2-Q1 UNIT
PWP (HTSSOP)
28 Pins
θJA Junction-to-ambient thermal resistance 30.3 °C/W
θJCtop Junction-to-case (top) thermal resistance 33.5 °C/W
θJB Junction-to-board thermal resistance 17.5 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 7.2 °C/W
θJCbot Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

6.5 DC Characteristics

TA = –40°C to 125°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
| VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB 1.5 15 mV
ICC Quiescent supply current SD = 2 V, no load, PVCC = 24 V 32 50 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 24 V 250 400 µA
rDS(on) Drain-source on-state resistance VCC = 12 V, IO = 500 mA,
TJ = 25°C		 High side 240 mΩ
Low side 240
G Gain GAIN1 = 0.8 V GAIN0 = 0.8 V 19 20 21 dB
GAIN0 = 2 V 25 26 27
GAIN1 = 2 V GAIN0 = 0.8 V 31 32 33 dB
GAIN0 = 2 V 35 36 37
ton Turn-on time SD = 2 V 14 ms
tOFF Turn-off time SD = 0.8 V 2 μs
GVDD Gate drive supply IGVDD = 100 μA 6.4 6.9 7.4 V
tDCDET DC detect time V(RINN) = 6 V, VRINP = 0 V 420 ms

6.6 DC Characteristics

TA = –40°C to 125°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
| VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB 1.5 15 mV
ICC Quiescent supply current SD = 2 V, no load, PVCC = 12 V 20 35 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 12 V 200 µA
rDS(on) Drain-source on-state resistance VCC = 12 V, IO = 500 mA,
TJ = 25°C		 High side 240 mΩ
Low side 240
G Gain GAIN1 = 0.8 V GAIN0 = 0.8 V 19 20 21 dB
GAIN0 = 2 V 25 26 27
GAIN1 = 2 V GAIN0 = 0.8 V 31 32 33 dB
GAIN0 = 2 V 35 36 37
tON Turn-on time SD = 2 V 14 ms
tOFF Turn-off time SD = 0.8 V 2 μs
GVDD Gate drive supply IGVDD = 2 mA 6.4 6.9 7.4 V
VO Output voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1 VRMS 6.75 7.90 8.75 V

6.7 AC Characteristics

TA = –40°C to 125°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
KSVR Power supply ripple rejection 200 mVPP ripple at 1 kHz,
Gain = 20 dB, inputs AC-coupled to AGND		 –70 dB
PO Continuous output power THD+N = 10%, f = 1 kHz, VCC = 16 V 15 W
THD+N Total harmonic distortion + noise VCC = 16 V, f = 1 kHz, PO = 7.5 W (half-power) 0.1%
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB 65 µV
–80 dBV
Crosstalk VO = 1 VRMS, Gain = 20 dB, f = 1 kHz –100 dB
SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted		 102 dB
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C

6.8 AC Characteristics

TA = –40°C to 125°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
KSVR Supply ripple rejection 200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, inputs AC-coupled to AGND		 –70 dB
PO Continuous output power THD+N = 10%, f = 1 kHz; VCC = 13 V 10 W
THD+N Total harmonic distortion + noise RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power) 0.06%
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB 65 µV
–80 dBV
Crosstalk Po = 1 W, Gain = 20 dB, f = 1 kHz –100 dB
SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted		 102 dB
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C

6.9 Typical Characteristics

All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the measurements.
TPA3110D2-Q1 g001_los528.gif
Figure 1. Total Harmonic Distortion vs Frequency (BTL)
TPA3110D2-Q1 g003_los528.gif
Figure 3. Total Harmonic Distortion vs Frequency (BTL)
TPA3110D2-Q1 g005_los528.gif
Figure 5. Total Harmonic Distortion vs Frequency (BTL)
TPA3110D2-Q1 g007_los528.gif
Lighter color represents thermally limited region.
Figure 7. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3110D2-Q1 g009_los528.gif
Figure 9. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3110D2-Q1 g011_los528.gif
Figure 11. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3110D2-Q1 g013_los528.gif
Figure 13. Maximum Output Power vs PLIMIT Voltage (BTL)
TPA3110D2-Q1 g015_los528.gif
Figure 15. Gain/Phase vs Frequency (BTL)
TPA3110D2-Q1 g017_los528.gif
Note: Dashed lines represent thermally limited regions.
Figure 17. Output Power vs Supply Voltage (BTL)
TPA3110D2-Q1 g032_los528.gif
Figure 19. Efficiency vs Output Power (BTL With LC Filter)
TPA3110D2-Q1 g033_los528.gif
Figure 21. Efficiency vs Output Power (BTL With LC Filter)
TPA3110D2-Q1 g034_los528.gif
Figure 23. Efficiency vs Output Power (BTL With LC Filter)
TPA3110D2-Q1 g022_los528.gif
Note: Dashed lines represent thermally limited regions.
Figure 25. Supply Current vs Total Output Power (BTL)
TPA3110D2-Q1 g024_los528.gif
Figure 27. Supply Ripple Rejection Ratio vs Frequency (BTL)
TPA3110D2-Q1 g026_los528.gif
Figure 29. Total Harmonic Distortion + Noise vs Output Power (PBTL)
TPA3110D2-Q1 g028_los528.gif
Note: Dashed lines represent thermally limited regions.
Figure 31. Output Power vs Supply Voltage (PBTL)
TPA3110D2-Q1 g030_los528.gif
Figure 33. Supply Current vs Output Power (PBTL)
TPA3110D2-Q1 g002_los528.gif
Figure 2. Total Harmonic Distortion vs Frequency (BTL)
TPA3110D2-Q1 g004_los528.gif
Figure 4. Total Harmonic Distortion vs Frequency (BTL)
TPA3110D2-Q1 g006_los528.gif
Figure 6. Total Harmonic Distortion vs Frequency (BTL)
TPA3110D2-Q1 g008_los528.gif
Figure 8. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3110D2-Q1 g010_los528.gif
Figure 10. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3110D2-Q1 g012_los528.gif
Figure 12. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3110D2-Q1 g014_los528.gif
Note: Dashed lines represent thermally limited regions.
Figure 14. Output Power vs PLIMIT Voltage (BTL)
TPA3110D2-Q1 g016_los528.gif
Note: Dashed lines represent thermally limited regions.
Figure 16. Output Power vs Supply Voltage (BTL)
TPA3110D2-Q1 g018_los528.gif
Note: Dashed lines represent thermally limited regions.
Figure 18. Efficiency vs Output Power (BTL)
TPA3110D2-Q1 g019_los528.gif
Note: Dashed lines represent thermally limited regions.
Figure 20. Efficiency vs Output Power (BTL)
TPA3110D2-Q1 g020_los528.gif
Figure 22. Efficiency vs Output Power (BTL)
TPA3110D2-Q1 g021_los528.gif
Note: Dashed lines represent thermally limited regions.
Figure 24. Supply Current vs Total Output Power (BTL)
TPA3110D2-Q1 g023_los528.gif
Figure 26. Crosstalk vs Frequency (BTL)
TPA3110D2-Q1 g025_los528.gif
Figure 28. Total Harmonic Distortion vs Frequency (PBTL)
TPA3110D2-Q1 g027_los528.gif
Figure 30. Gain/Phase vs Frequency (PBTL)
TPA3110D2-Q1 g029_los528.gif
Figure 32. Efficiency vs Output Power (PBTL)
TPA3110D2-Q1 g031_los528.gif
Figure 34. Supply Ripple Rejection Ratio vs Frequency (PBTL)

7 Detailed Description

7.1 Overview

The TPA3110D2-Q1 is AEC-Q100 qualified with a temperature grade 1 (-40°C to 125°C), HBM ESD classification level H2, and CDM ESD classification level C2. This automotive audio amplifier also features several protection mechanisms as follows:

  • DC Current Detection
    • The TPA3110D2-Q1 protects speakers from DC current by reporting a fault on the FAULT pin and turning the amplifier outputs to a Hi-Z state when a DC current is detected. The PVCC supply must be cycled to clear this fault.
  • Short-Circuit Protection and Automatic Recovery
    • The TPA3110D2-Q1 has short circuit protection from the output pins to VCC, GND, or to each other. If a short circuit is detected, it will be reported on the FAULT pin and the amplifier outputs will be switched to a Hi-Z state. The fault can be cleared by cycling the SD pin.
  • Thermal Protection
    • When the die temperature exceeds 150°C (±15°C) the device enters the shutdown state and the amplifier outputs are disabled. The TPA3110D2-Q1 recovers automatically when the temperature decreases by 15°C

7.2 Functional Block Diagram

TPA3110D2-Q1 int_bd_los528.gif

7.3 Feature Description

7.3.1 DC Detect

TPA3110D2-Q1 has circuitry which protects the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault is reported on the FAULT pin as a low state. The DC detect fault also causes the amplifier to shut down by changing the state of the outputs to Hi-Z. To clear the DC detect it is necessary to cycle the PVCC supply. Cycling SD does NOT clear a DC detect fault.

A DC detect fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example, 57%, –43%) for more than 420 msec at the same polarity. This feature protects the speaker from large DC currents or AC currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults.

The minimum differential input voltages required to trigger the DC detect are shown in Table 1. The inputs must remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect.

Table 1. DC Detect Threshold

AV (dB) VIN (mV, Differential)
20 112
26 56
32 28
36 17

7.3.2 Short-Circuit Protection and Automatic Recovery Feature

TPA3110D2-Q1 has protection from overcurrent conditions caused by a short circuit on the output stage. The short-circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short-circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state.

If automatic recovery from the short-circuit protection latch is desired, connect the FAULT pin directly to the SD pin. This allows the FAULT pin function to automatically drive the SD pin low, which clears the short-circuit protection latch.

7.3.3 Thermal Protection

Thermal protection on the TPA3110D2-Q1 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device begins normal operation at this point with no external system interaction.

Thermal protection faults are NOT reported on the FAULT terminal.

7.3.4 GVDD Supply

The GVDD supply is used to power the gates of the output full bridge transistors. It can also be used to supply the PLIMIT voltage divider circuit. Add a 1-μF capacitor to ground at this pin.

7.4 Device Functional Modes

7.4.1 PBTL Select

Use the PBTL pin to select between PBTL mode when held high or BTL mode when held low. Connect the speaker between the right and left outputs, with the positive and negative output from each channel tied together.

7.4.2 Gain Setting Through GAIN0 and GAIN1 Inputs

The gain of the TPA3110D2-Q1 is set to one of four options by the state of the GAIN0 and GAIN1 pins. Changing the gain setting also changes the input impedance of the TPA3110D2-Q1.

Refer to Table 2 for a list of the gain settings.

Table 2. Gain Setting

GAIN1 GAIN0 AMPLIFIER GAIN (dB) INPUT IMPEDANCE (kΩ)
TYP TYP
0 0 20 60
0 1 26 30
1 0 32 15
1 1 36 9

7.4.3 SD Operation

The SD pin can be used to enter the shutdown mode which mutes the amplifier and causes the TPA3110D2-Q1 to enter a low-current state. This mode can also be triggered to improve power-off pop performance.

7.4.4 PLIMIT

The PLIMIT pin limits the output peak-to-peak voltage based on the voltage supplied to the PLIMIT pin. The peak output voltage is limited to four times the voltage at the PLIMIT pin.

TPA3110D2-Q1 pwr_lim_los528.gif Figure 35. PLIMIT Circuit Operation

The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply connected to PVCC. This virtual rail is four times the voltage at the PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.

Equation 1. TPA3110D2-Q1 q_plimit_los528.gif

Where:

RS is the total series resistance including RDS(on), and any resistance in the output filter.

RL is the load resistance.

VP is the peak amplitude of the output possible within the supply rail.

VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP

POUT (10%THD) = 1.25 × POUT (unclipped)

Table 3. PLIMIT Typical Operation

TEST CONDITIONS PLIMIT VOLTAGE OUTPUT POWER (W) Output Voltage Amplitude (VP-P)
PVCC = 24 V, VIN = 1 VRMS,
RL = 8 Ω, Gain = 26 dB		 6.97 36.1 (thermally limited) 43
PVCC = 24 V, VIN = 1 VRMS,
RL = 8 Ω, Gain = 26 dB		 2.94 15 25.2
PVCC = 24 V, VIN = 1 VRMS,
RL = 8 Ω, Gain = 26 dB		 2.34 10 20
PVCC = 24 V, VIN = 1 VRMS,
RL = 8 Ω, Gain = 26 dB		 1.62 5 14
PVCC = 24 V, VIN = 1 VRMS,
RL = 8 Ω, Gain = 20 dB		 6.97 12.1 27.7
PVCC = 24 V, VIN = 1 VRMS,
RL = 8 Ω, Gain = 20 dB		 3 23
PVCC = 24 V, VIN = 1 VRMS,
RL = 8 Ω, Gain = 20 dB		 1.86 5 14.8
PVCC = 12 V, VIN = 1 VRMS,
RL = 8 Ω, Gain = 20 dB		 6.97 10.55 23.5
PVCC = 12 V, VIN = 1 VRMS,
RL = 8 Ω, Gain = 20 dB		 1.76 5 15

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale