TPA3221 is a high-power Class-D amplifier that enables efficient operation at full-power, idle and standby. The device features closed-loop feedback with a bandwidth up to 100 kHz, which provides low distortion across the audio band and delivers excellent sound quality. The device operates with either AD or low idle-current HEAD (High Efficient AD mode) modulation, and can drive up to 2 x 105 W into 4-Ω load or 1 x 208 W into 2-Ω load.
The TPA3221 features a single-ended or differential analog-input interface that supports up to 2 VRMS with four selectable gains: 18 dB, 24 dB, 30 dB and 34 dB. The TPA3221 also achieves >90% efficiency, low idle power (<0.25 W) and ultra-low standby power (<0.1 W). This is made possible through the use of 70-mΩ MOSFETs, an optimized gate drive scheme and low-power operating modes. TPA3221 includes a built-in LDO for easy integration in single-power-supply systems. To further simplify the design, the device integrates essential protection features including undervoltage, overvoltage, cycle-by-cycle current limit, short circuit, clipping detection, overtemperature warning and shutdown, as well as DC speaker protection.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPA3221 | HTSSOP (44) | 6.10 mm x 14.00 mm |
Changes from A Revision (November 2017) to B Revision
Changes from * Revision (September 2017) to A Revision
DEVICE NAME | DESCRIPTION | THERMAL PAD LOCATION |
TPA3221 PIN-COMPATIBLE |
TPA3220 | 35 W Stereo, 100 W Peak HD-Audio, Analog-Input, Class-D Amplifier | Bottom | Y |
TPA3244 | 40 W Stereo, 100 W Peak Ultra-HD, Analog-Input Class-D Amplifier | Bottom | |
TPA3245 | 100 W Stereo, 200 W Mono Ultra-HD, Analog-Input Class-D Amplifier | Top | |
TPA3250 | 70 W Stereo, 130 W Peak Ultra-HD, Analog-Input Class-D Amplifier | Bottom | |
TPA3251 | 175 W Stereo, 350 W Mono Ultra-HD, Analog-Input Class-D Amplifier | Top | |
TPA3255 | 315 W Stereo, 600 W Mono Ultra-HD, Analog-Input Class-D Amplifier | Top |
The TPA3221 is available in a thermally enhanced TSSOP package.
The package type contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heat sink.
NAME | NO. | I/O | DESCRIPTION |
---|---|---|---|
HEAD | 11 | I | 0 = AD, 1 = HEAD. Refer to: AD-Mode and HEAD-Mode PWM Modulation |
AVDD | 21 | P | AVDD voltage supply. Refer to: Internal LDO, AVDD and GVDD Supplies |
BST1_M | 43 | P | OUT1_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_M required. Refer to: BST capacitors |
BST1_P | 44 | P | OUT1_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_P required. Refer to: BST capacitors |
BST2_M | 23 | P | OUT2_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_M required. Refer to: BST capacitors |
BST2_P | 24 | P | OUT2_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_P required. Refer to: BST capacitors |
CMUTE | 17 | P | Mute and Startup Timing Capacitor. Connect a 33 nF capacitor to GND. Refer to: Device Reset |
FAULT | 4 | O | Shutdown signal, open drain; active low. Refer to: Error Reporting |
FREQ_ADJ | 14 | O | Oscillator frequency programming pin. Refer to: Oscillator |
GAIN/SLV | 2 | I | Closed loop gain and master/slave programming pin. Refer to: Input Configuration, Gain Setting And Master / Slave Operation |
GND | 5, 6, 7, 18, 19, 20, 25, 26, 33, 34, 41, 42 | P | Ground |
GVDD | 22 | P | Gate drive supply. Refer to: Internal LDO, AVDD and GVDD Supplies |
IN1_M | 9 | I | Negative audio input for channel 1 |
IN1_P | 8 | I | Positive audio input for channel 1 |
IN2_M | 16 | I | Negative audio input for channel 2 |
IN2_P | 15 | I | Positive audio input for channel 2 |
OSCM | 12 | I/O | Oscillator synchronization interface. Refer to: Input Configuration, Gain Setting And Master / Slave Operation |
OSCP | 13 | I/O | Oscillator synchronization interface. Refer to: Input Configuration, Gain Setting And Master / Slave Operation |
OTW_CLIP | 3 | O | Clipping warning and Over-temperature warning; open drain; active low. Refer to: Error Reporting |
OUT1_M | 35 | O | Negative output for channel 1 |
OUT1_P | 39, 40 | O | Positive output for channel 1 |
OUT2_M | 27, 28 | O | Negative output for channel 2 |
OUT2_P | 32 | O | Positive output for channel 2 |
PVDD | 29, 30, 31, 36, 37, 38 | P | PVDD supply. Refer to: PVDD Capacitor Recommendation, PVDD Supply |
RESET | 10 | I | Device reset Input; active low. Refer to: Fault Handling, Powering Up, Powering Down |
VDD | 1 | P | Input power supply. Refer to: Internal LDO, VDD Supply |
PowerPad™ | P | Ground, connect to grounded heatsink. Placed on top side of device. |
MODE PINS(2) | INPUT MODE(1) | OUTPUT CONFIGURATION | DESCRIPTION | ||||
---|---|---|---|---|---|---|---|
IN2_M | IN2_P | HEAD | |||||
X | X | 0 | 1N/2N + 1 | 2 × BTL | Stereo, BTL output configuration, AD mode modulation | ||
X | X | 1 | 1N/2N + 1 | 2 × BTL | Stereo, BTL output configuration, HEAD mode modulation | ||
0 | 0 | 0 | 1N/2N + 1 | 1 x PBTL | Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, AD mode modulation | ||
0 | 0 | 1 | 1N/2N + 1 | 1 x PBTL | Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, HEAD mode modulation | ||
1 | 1 | 0 | 1N/2N + 1 | 1 x BTL | Mono, BTL configuration. OUT1_M and OUT1_P active, AD mode modulation | ||
1 | 1 | 1 | 1N/2N + 1 | 1 x BTL | Mono, BTL configuration. OUT1_M and OUT1_P active, HEAD mode modulation |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | PVDD to GND(2) | –0.3 | 37 | V |
BST_X to GVDD(2) | –0.3 | 37 | V | |
BST1_M, BST1_P, BST2_M, BST2_P to GND(2) | –0.3 | 47.8 | V | |
VDD to GND | –0.3 | 43 | V | |
GVDD to GND(2) | –0.3 | 5.5 | V | |
AVDD to GND | –0.3 | 5.5 | V | |
Interface pins | OUT1_M, OUT1_P, OUT2_M, OUT2_P to GND(2) | –0.3 | 43 | V |
IN1_M, IN1_P, IN2_M, IN2_P to GND | –0.3 | 5.5 | V | |
HEAD, FREQ_ADJ, GAIN/SLV, CMUTE, RESET, OSCP, OSCM to GND | –0.3 | 5.5 | V | |
FAULT, OTW_CLIP to GND | –0.3 | 5.5 | V | |
Continuous sink current, FAULT, OTW_CLIP to GND | 9 | mA | ||
TJ | Operating junction temperature range | –40 | 150 | °C |
Tstg | Storage temperature range | –40 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
VESD | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) | ±1000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±250 | V |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
PVDD | Power-stage supply | DC supply voltage | 7 | 30 | 32 | V |
VDD(1) | Supply voltage for internal LDO regulator to supply GVDD and AVDD | DC supply voltage | 7 | 32 | V | |
External supply for VDD, GVDD and AVDD. Internal LDO bypassed | DC supply voltage | 4.5 | 5 | 5.5 | V | |
AVDD | Supply voltage for analog circuits | DC supply voltage | 4.5 | 5 | 5.5 | V |
GVDD | Supply voltage for gate-drive circuitry | DC supply voltage | 4.5 | 5 | 5.5 | V |
LOUT(BTL) | Output filter inductance | Minimum output inductance at IOC | 5 | 10 | μH | |
LOUT(PBTL) | Output filter inductance, PBTL before the LC filter | Minimum output inductance at IOC | 5 | 10 | ||
Output filter inductance, PBTL after the LC filter | Minimum output inductance at half IOC , each inductor | 5 | 10 | |||
FPWM | PWM frame rate selectable for AM interference avoidance; 1% Resistor tolerance | Nominal | 575 | 600 | 625 | kHz |
AM1 | 510 | 533 | 555 | |||
AM2 | 460 | 480 | 500 | |||
R(FREQ_ADJ) | PWM frame rate programming resistor | Nominal; Master mode | 49.5 | 50 | 50.5 | kΩ |
AM1; Master mode | 29.7 | 30 | 30.3 | |||
AM2; Master mode | 9.9 | 10 | 10.1 | |||
CPVDD | PVDD close decoupling capacitors | 1.0 | μF | |||
V(FREQ_ADJ) | Voltage on FREQ_ADJ pin for slave mode operation | Slave Mode (Connect to AVDD) | 5 | V |
THERMAL METRIC(1) | TPA3221 | UNIT | ||
---|---|---|---|---|
DDV 44-PINS HTSSOP | ||||
JEDEC STANDARD 4 LAYER PCB | FIXED 85°C HEATSINK TEMPERATURE(2) | |||
RθJA | Junction-to-ambient thermal resistance | 44.8 | 5.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 1.1 | 2.0 | °C/W |
RθJB | Junction-to-board thermal resistance | 14.9 | n/a | °C/W |
ψJT | Junction-to-top characterization parameter | 0.6 | n/a | °C/W |
ψJB | Junction-to-board characterization parameter | 14.7 | n/a | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION |
||||||
AVDD | Voltage regulator. Only used as reference node when supplied by internal LDO. Voltage regulator bypassed for VDD = 5 V. | VDD = 30 V | 5 | V | ||
IVDD | VDD supply current. LDO mode (VDD > 7 V) | Operating, no audio signal | 25 | mA | ||
Reset mode | 118 | µA | ||||
VDD supply current. LDO bypass mode (VDD = 5 V) | Operating, no audio signal | 150 | ||||
Reset mode | 50 | |||||
IAVDD | Gate-supply current. LDO bypass mode (VDD = 5 V) | Operating, no audio signal | 10 | mA | ||
Reset mode | 1 | |||||
IGVDD | Gate-supply current. LDO bypass mode (VDD = 5 V), AD-mode modulation | 50% duty cycle | 16 | |||
Reset mode | 50 | µA | ||||
Gate-supply current. LDO bypass mode (VDD = 5 V), HEAD-mode modulation | HEAD-mode modulation | 16 | mA | |||
Reset mode | 50 | µA | ||||
IPVDD | Total PVDD idle current, AD-mode modulation, BTL | 50% duty cycle with recommended output filter | 15 | mA | ||
50% duty cycle with recommended output filter, TC = 25 ºC | 13 | |||||
Reset mode, No switching | 1 | |||||
Total PVDD idle current, HEAD-mode modulation, BTL | HEAD-mode modulation with recommended output filter | 10 | ||||
HEAD-mode with recommended output filter, TC = 25 ºC | 9 | |||||
Reset mode, No switching | 1 | |||||
ANALOG INPUTS | ||||||
VIN | Maximum input voltage swing | ±2.8 | V | |||
IIN | Maximum input current | -1 | 1 | mA | ||
G | Inverting voltage Gain, VOUT/VIN(Master Mode) | R1 = 5.6 kΩ, R2 = OPEN | 18 | dB | ||
R1 = 20 kΩ, R2 = 100 kΩ | 24 | |||||
R1 = 39 kΩ, R2 = 100 kΩ | 30 | |||||
R1 = 47 kΩ, R2 = 75 kΩ | 34 | |||||
Inverting voltage Gain, VOUT/VIN(Slave Mode) | R1 = 51 kΩ, R2 = 51 kΩ | 18 | ||||
R1 = 75 kΩ, R2 = 47 kΩ | 24 | |||||
R1 = 100 kΩ, R2 = 39 kΩ | 30 | |||||
R1 = 100 kΩ, R2 = 16 kΩ | 34 | |||||
RIN | Input resistance | G = 18 dB | 48 | kΩ | ||
G = 24 dB | 24 | |||||
G = 30 dB | 12 | |||||
G = 34 dB | 7.7 | |||||
OSCILLATOR | ||||||
fOSC(IO) (1) | Nominal, Master Mode | FPWM × 6 | 3.45 | 3.6 | 3.75 | MHz |
AM1, Master Mode | 3.06 | 3.198 | 3.33 | |||
AM2, Master Mode | 2.76 | 2.88 | 3 | |||
VIH | High level input voltage | 1.88 | V | |||
VIL | Low level input voltage | 1.65 | V | |||
EXTERNAL OSCILLATOR (Slave Mode) | ||||||
fOSC(IO) | CLK input on OSCM/OSCP (Slave Mode) | 2.3 | 3.78 | MHz | ||
OUTPUT-STAGE MOSFETs |
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RDS(on) | Drain-to-source resistance, low side (LS) | TJ = 25 °C, Excludes metallization resistance, GVDD = 5 V |
70 | mΩ | ||
Drain-to-source resistance, high side (HS) | 70 | mΩ | ||||
I/O PROTECTION | ||||||
Vuvp,AVDD | Undervoltage protection limit, AVDD | 4 | V | |||
Vuvp,AVDD,hyst (2) | Undervoltage protection hysteresis, AVDD | 0.1 | V | |||
Vuvp,PVDD | Undervoltage protection limit, PVDD_x | 6.4 | V | |||
Vuvp,PVDD,hyst (2) | Undervoltage protection hysteresis, PVDD_x | 0.45 | V | |||
Vovp,PVDD | Overvoltage protection limit, PVDD_x | 34 | V | |||
Vovp,PVDD,hyst (2) | Overvoltage protection hysteresis, PVDD_x | 0.45 | V | |||
OTW | Overtemperature warning, OTW_CLIP (2) | 115 | 125 | 135 | °C | |
OTWhyst (2) | Temperature drop needed below OTW temperature for OTW_CLIP to be inactive after OTW event. | 20 | °C | |||
OTE(2) | Overtemperature error | 145 | 155 | 165 | °C | |
OTEhyst (2) | A reset needs to occur for FAULT to be released following an OTE event | 20 | °C | |||
OTE-OTW(differential) (2) | OTE-OTW differential | 25 | °C | |||
OLPC | Overload protection counter | fPWM = 600 kHz (1024 PWM cycles) | 1.7 | ms | ||
IOC, BTL | Overcurrent limit protection, speaker output current | Nominal peak current in 1Ω load | 10 | A | ||
IOC, PBTL | 20 | A | ||||
IDCspkr, BTL | DC Speaker Protection Current Threshold | BTL current imbalance threshold | 1.8 | A | ||
IDCspkr, PBTL | PBTL current imbalance threshold | 3.6 | A | |||
IOCT | Overcurrent response time | Time from switching transition to flip-state induced by overcurrent. | 150 | ns | ||
IPD | Output pulldown current of each half | Connected when RESET is active to provide bootstrap charge. Not used in SE mode. | 3 | mA | ||
STATIC DIGITAL SPECIFICATIONS | ||||||
VIH | High level input voltage | HEAD, OSCM, OSCP,CMUTE, RESET | 1.9 | V | ||
VIL | Low level input voltage | 0.8 | V | |||
Ilkg | Input leakage current | 100 | μA | |||
OTW/SHUTDOWN (FAULT) | ||||||
RINT_PU | Internal pullup resistance, OTW_CLIP to AVDD, FAULT to AVDD | 20 | 26 | 32 | kΩ | |
VOH | High level output voltage | Internal pullup resistor | 3 | 3.3 | 3.6 | V |
VOL | Low level output voltage | IO = 4 mA | 200 | 500 | mV | |
Device fanout | OTW_CLIP, FAULT | No external pullup | 30 | devices |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PO | Power output per channel | RL = 3 Ω, 10% THD+N | 112 | W | ||
RL = 4 Ω, 10% THD+N | 105 | |||||
RL = 3 Ω, 1% THD+N | 100 | |||||
RL = 4 Ω, 1% THD+N | 88 | |||||
THD+N | Total harmonic distortion + noise | 1 W | 0.02 | % | ||
Vn | Output integrated noise | A-weighted, AES17 filter, Input Capacitor Grounded, Gain = 18 dB | 75 | μV | ||
|VOS| | Output offset voltage | Inputs AC coupled to GND | 20 | 60 | mV | |
SNR | Signal-to-noise ratio(1) | A-weighted, Gain = 18 dB | 108 | dB | ||
DNR | Dynamic range | A-weighted, Gain = 18 dB | 109 | dB | ||
Pidle | Power dissipation due to idle losses (IPVDD_X) | PO = 0, all outputs switching, AD-modulation, TC = 25°C(2) | 0.37 | W | ||
PO = 0, all outputs switching, HEAD-modulation, TC = 25°C(2) | 0.25 | W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PO | Power output per channel | RL = 2 Ω, 10% THD+N | 208 | W | ||
RL = 3 Ω, 10% THD+N | 155 | |||||
RL = 4 Ω, 10% THD+N | 120 | |||||
RL = 2 Ω, 1% THD+N | 170 | |||||
RL = 3 Ω, 1% THD+N | 125 | |||||
RL = 4 Ω, 1% THD+N | 98 | |||||
THD+N | Total harmonic distortion + noise | 1 W | 0.02 | % | ||
Vn | Output integrated noise | A-weighted, AES17 filter, Input Capacitor Grounded, Gain = 18 dB | 75 | μV | ||
|VOS| | Output offset voltage | Inputs AC coupled to GND | 20 | 60 | mV | |
SNR | Signal to noise ratio(1) | A-weighted, Gain = 18 dB | 108 | dB | ||
DNR | Dynamic range | A-weighted, Gain = 18 dB | 110 | dB | ||
Pidle | Power dissipation due to idle losses (IPVDD_X) | PO = 0, all outputs switching, AD-modulation, TC = 25°C(2) | 0.20 | W | ||
PO = 0, all outputs switching, HEAD-modulation, TC = 25°C(2) | 0.17 | W |
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, RL = 4 Ω, fS = 600 kHz, 18 dB, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, AD-Modulation, AES17 + AUX-0025 measurement filters, unless otherwise noted.
18 kHz + 19 kHz | Ratio 1 : 1 |
18 kHz + 19 kHz | Ratio 1 : 1 |
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, RL = 2 Ω, fS = 600 kHz, 18 dB, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, Pre-Filter PBTL, AD Modulation, AES17 + AUX-0025 measurement filters, unless otherwise noted.
18 kHz + 19 kHz | Ratio 1 : 1 |
18 kHz + 19 kHz | Ratio 1 : 1 |