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  • TPD12S015A HDMI Companion Chip With Step-Up DC-DC, I2C Level Shifter, and High-Speed ESD Clamps

    • SLLSE74D June   2011  – July 2016 TPD12S015A

      PRODUCTION DATA.  

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  • TPD12S015A HDMI Companion Chip With Step-Up DC-DC, I2C Level Shifter, and High-Speed ESD Clamps
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ICC
    6. 6.6  Electrical Characteristics: High-Speed ESD Lines: Dx, CLK
    7. 6.7  Electrical Characteristics: DC-DC Converter
    8. 6.8  Electrical Characteristics: Passive Components
    9. 6.9  Electrical Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A/x_B Ports)
    10. 6.10 Electrical Characteristics: Voltage Level Shifter: CEC Lines (x_A/x_B Ports)
    11. 6.11 Electrical Characteristics: Voltage Level Shifter: HPD Line (x_A/x_B Ports)
    12. 6.12 Electrical Characteristics: LS_OE, CT_CP_HPD
    13. 6.13 Electrical Characteristics: I/O Capacitance
    14. 6.14 Switching Characteristics
    15. 6.15 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.2 V
    16. 6.16 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.2 V
    17. 6.17 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.2 V
    18. 6.18 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.5 V
    19. 6.19 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.5 V
    20. 6.20 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.5 V
    21. 6.21 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.8 V
    22. 6.22 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.8 V
    23. 6.23 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.8 V
    24. 6.24 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 2.5 V
    25. 6.25 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 2.5 V
    26. 6.26 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 2.5 V
    27. 6.27 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 3.3 V
    28. 6.28 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 3.3 V
    29. 6.29 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 3.3 V
    30. 6.30 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rise-Time Accelerators
      2. 8.3.2 Internal Pullup Resistor
      3. 8.3.3 Undervoltage Lockout
      4. 8.3.4 Soft Start
      5. 8.3.5 DDC/CEC Level Shifting Function
      6. 8.3.6 DDC/CEC Level Shifting Function When VCCA = 1.8 V
      7. 8.3.7 CEC Level Shifting Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable
      2. 8.4.2 Power Save Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 CEC, HPD, SCL, SDA Level Shifting Function
        5. 9.2.2.5 ESD
        6. 9.2.2.6 Ground Offset Consideration
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • YFF|28
    • MXBG108N
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sllse74d_oa
  • sllse74d_pm
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    • Full reading width
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    • Expanded reading width
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DATA SHEET

TPD12S015A HDMI Companion Chip With Step-Up DC-DC, I2C Level Shifter, and High-Speed ESD Clamps

1 Features

  • Conforms to HDMI Compliance Tests Without Any External Components
  • Supports HDMI 1.3 and HDMI 1.4 Data Rate
  • Match Class D and Class C Pin Mapping
  • Excellent Matching Capacitance (0.05 pF) in Each Differential Signal Pair
  • Internal Boost Converter to Generate 5 V From a 2.3-V to 5.5-V Battery Voltage
  • Auto-Direction Sensing Level Shifting in the CEC, SDA, and SCL Paths
  • IEC 61000-4-2 (Level 4) System Level ESD Compliance
  • Improved Drop-In Replacement for the Industry Popular TPD12S015A
  • Industrial Temperature Range: –40°C to 85°C

2 Applications

  • Smart Phones
  • eBooks
  • Tablet PCs
  • Digital Camcorders
  • Portable Game Consoles
  • Digital Still Cameras

SCL_B or SDA_B Buffers of TPD12S015A Driving Long HDMI Cable (750-pF Load)

TPD12S015A DCC_llse74.gif

3 Description

The TPD12S015A device is an integrated HDMI companion chip solution. This device offers 8 low capacitance ESD clamps allowing HDMI 1.3/1.4 data rates. The 0.4-mm pitch DSBGA package pin mapping matches the HDMI Type D or Type C connectors. The integrated ESD clamps in monolithic silicon technology provide good matching between each differential signal pair. This provides an advantage over discrete ESD clamp solutions where variations between ESD clamps degrade the differential signal quality.

The TPD12S015A provides a regulated 5-V output (5VOUT) for sourcing the HDMI power line. The 5VOUT pin supplies minimum 55 mA to the HDMI receiver while meeting the HDMI 5VOUT specifications. The 5VOUT and the hot plug detect (HPD) circuitry are independent of the LS_OE control signal; they are controlled by the CT_CP_HPD pin. This independent control enables the detection scheme (5VOUT + HPD) to be active before enabling the HDMI link. The HPD_B port has a glitch filter to avoid false detection due to the bouncing while inserting the HDMI plug.

There are three noninverting bidirectional translation circuits for the SDA, SCL, and CEC lines; they are controlled by the LS_OE control signal. Each have a common power rail (VCCA) on the A side from 1.1 V to 3.6 V. On the B side, the SCL_B and SDA_B each have an internal 1.75-kΩ pullup connected to the regulated 5-V rail (5VOUT). The SCL and SDA pins meet the I2C specifications, and drive at least 750-pF loads which exceeds the HDMI cable specification. An LDO generates a 3.3-V internal rail for the CEC line operation when LS_OE = H & CT_CP_HPD = H. The CEC_B pin has a 26-kΩ pullup to this internal 3.3-V rail.

The TPD12S015A provides IEC61000-4-2 (Level 4) ESD protection. This device is offered in a space-saving 1.56-mm × 2.76-mm DSBGA package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPD12S015A DSBGA (28) 1.56 mm × 2.76 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

4 Revision History

Changes from C Revision (March 2013) to D Revision

  • Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo

Changes from B Revision (April 2012) to C Revision

  • Added Power Derating CurveGo
  • Changed Board Layout sectionGo

5 Pin Configuration and Functions

YFF Package
28-Pin DSBGA
Top View
TPD12S015A po_llse19.gif
For package dimensions, see Mechanical, Packaging, and Orderable Information

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
5VOUT F1 Power Out DC-DC output. The 5-V power pin can supply 55 mA of regulated current to the HDMI receiver. Separate DC-DC converter control pin CT_CP_HPD disables the DC-DC converter when operating at low-power mode.
CEC_A B2 I/O System-side CEC bus I/O. This pin is bidirectional and referenced to VCCA.
CEC_B D3 I/O HDMI-side CEC bus I/O. This pin is bidirectional and referenced to the 3.3-V internal supply.
CLK–, CLK+ G4, F4 ESD High-speed ESD clamp: provides ESD protection to the high-speed HDMI differential data lines
CT_CP_HPD D1 Control DC-DC Enable. Enables the DC-DC converter and HPD circuitry when CT_CP_HPD = H. The CT_CP_HPD is referenced to VCCA.
D0–, D0+,
D1– , D1+,
D2–, D2+ 		E4, D4,
C4, B4,
A4, A3		 ESD High-speed ESD clamp: provides ESD protection to the high-speed HDMI differential data lines
FB E1 I Feedback input. This pin is a feedback control pin for the DC-DC converter. It must be connected to 5VOUT.
GND B3, C3,
D2, E2		 Ground Device ground
HPD_A C2 O System-side output for the hot plug detect. This pin is unidirectional and is referenced to VCCA.
HPD_B G3 I HDMI-side input for the hot plug detect. This pin is unidirectional and is referenced to 5VOUT.
LS_OE A1 Control Level shifter enable. This pin is referenced to VCCA. Enables SCL, SDA, CEC level shifters, and LDO when LS_OE = H.
PGND G1 Analog Ground DC-DC converter ground. This pin must be tied externally to the system GND plane. See Layout Guidelines.
SCL_A B1 I/O System-side input and output for I2C bus. This pin is bidirectional and referenced to VCCA.
SCL_B E3 I/O HDMI-side input and output for I2C bus. This pin is bidirectional and referenced to 5VOUT.
SDA_A C1 I/O System-side input and output for I2C bus. This pin is bidirectional and referenced to VCCA.
SDA_B F3 I/O HDMI-side input and output for I2C bus. This pin is bidirectional and referenced to 5VOUT.
SW F2 I Switch input. This pin is the inductor input for the DC-DC converter.
VBAT G2 Supply Battery supply. This voltage is typically 2.3 V to 5.5 V
VCCA A2 Supply System-side supply. this voltage is typically 1.2 V to 3.3 V from the core microcontroller.

Table 1. YFF Package Pin Mapping

1 2 3 4
A LS_OE VCCA D2+ D2–
B SCL_A CEC_A GND D1+
C SDA_A HPD_A GND D1–
D CT_CP_HPD GND CEC_B D0+
E FB GND SCL_B D0–
F 5VOUT SW SDA_B CLK+
G PGND VBAT HPD_B CLK–

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCCA Supply voltage 4 V
VBAT Supply voltage –0.3 6
VI Input voltage HPD_B, Dx, CLKx –0.3 6 V
CT_CP_HPD, LS_OE –0.3 4
VO Voltage range applied to any output in the high-impedance or power-off state(2) SCL_A, SDA_A, CEC_A, HPD_A –0.3 4 V
SCL_B, SDA_B, CEC_B –0.3 6
Voltage range applied to any output in the high or low state(3) SCL_A, SDA_A, CEC_A, HPD_A –0.3 VCCA + 0.3
SCL_B, SDA_B, CEC_B –0.3 6
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IOUTMAX Continuous current through 5VOUT or GND ±100 mA
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins except B1, C1, B2, D1, A1, and A2 ±2500 V
Pins E4, D4, B4, C4, D2+, D2-, F4, G4, E3, F3, D3, G3, F1, and E1 ±15000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
IEC 61000-4-2 contact discharge Pins D4, E4, B4, C4, A3, A4, F4, G4, E3, F3, D3, G3, F1, E1 ±8000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over recommended operating free-air temperature range (unless otherwise noted)
SUPPLY MIN NOM MAX UNIT
VCCA Supply voltage 1.1 3.6 V
VBAT Supply voltage 2.3 5.5 V
VIH High-level input voltage SCL_A, SDA_A, CEC_A VCCA = 1.1 V to 3.6 V 0.7 × VCCA VCCA V
CT_CP_HPD, LS_OE 1 3.6
SCL_B, SDA_B 5VOUT = 5 V 0.7 × 5VOUT 5VOUT
CEC_B 0.7 × 3.3 (internal)(1) 3.3 (internal)(1)
HPD_B 2 5VOUT
VIL Low-level input voltage SCL_A, SDA_A, CEC_A VCCA = 1.1 V to 3.6 V 0 0.082 × VCCA V
CT_CP_HPD, LS_OE 0 0.4
SCL_B, SDA_B 5VOUT = 5 V 0 0.3 × 5VOUT
CEC_B 0 0.3 × 3.3V (internal)(1)
HPD_B 0 0.8
VILC Low-level input voltage (contention) SCL_A, SDA_A, CEC_A VCCA = 1.1 V to 3.6 V 0 0.065 × VCCA V
VOL – VILC Delta between VOL and VILC SCL_A, SDA_A, CEC_A VCCA = 1.1 V to 3.6 V 0.1 × VCCA V
TA Operating free-air temperature –40 85 °C
(1) '3.3V (internal)' is an internally generated voltage node for the CEC_B output buffer supply reference. An LDO generates this 3.3 V from 5VOUT when LS_OE = H & CT_CP_HPD = H.

6.4 Thermal Information

THERMAL METRIC(1) TPD12S015A UNIT
YFF (DSBGA)
28 PINS
RθJA Junction-to-ambient thermal resistance 63 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.4 °C/W
RθJB Junction-to-board thermal resistance 9.2 °C/W
ψJT Junction-to-top characterization parameter 1.6 °C/W
ψJB Junction-to-board characterization parameter 9.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: ICC

PARAMETER PIN TEST CONDITIONS MIN TYP MAX UNIT
ICCA Standby VCCA I/O = High 2 µA
Active 15
ICCB Standby VBAT CT_CP_HPD=L, LS_OE=L, HPD_B=L 2 µA
DC-DC and HPD active CT_CP_HPD=H, LS_OE=L, HPD_B=L 30 50
DC-DC, HPD, DDC, CEC active CT_CP_HPD=H LS_OE=H, HPD_B=L, I/O =H 225 300

6.6 Electrical Characteristics: High-Speed ESD Lines: Dx, CLK

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOFF Current from IO port to supply pins VCC = 0 V, VIO = 3.3 V 0.01 0.5 µA
VDL Diode forward voltage ID = 8 mA, Lower clamp diode 0.85 1 V
RDYN Dynamic resistance I = 1 A D, CLK 1 Ω
CIO IO capacitance VCC = 5 V
VIO = 2.5 V		 D, CLK 1.3 pF
VBR Break-down voltage IIO = 1 mA 9 12 V

6.7 Electrical Characteristics: DC-DC Converter

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBAT Input voltage range 2.3 5.5 V
5VOUT Total DC output voltage Includes voltage references, DC load / line regulations, process and temperature 4.9 5 5.13 V
TOVA Total output voltage accuracy Includes voltage references, DC load / line regulations, transient load / line regulations, ripple, process, and temperature 4.8 5 5.3 V
VO_Ripple Output voltage ripple, loaded IO = 65 mA 20 mVp-p
F_clk Internal operating frequency VBAT = 2.3 V to 5.5 V 3.5 MHz
tstart Start-up time From CT_CP_HPD input to 5-V power output 90% point 300 µs
IO Output current VBAT = 2.3 V to 5.5 V 55 mA
Reverse leakage current VO CT_CP_HPD= L, VO = 5.5 V 2.5 µA
Leakage current from battery to VO CT_CP_HPD= L 5 µA
VBATUVT Undervoltage lockout threshold Falling 2 V
Rising 2.1 V
VBATOVT Overvoltage lockout threshold Falling 5.9 V
Rising 6 V
Line transient response VBAT = 3.6 V, a pulse of 217-Hz 600 mVp-p square wave, IO = 20/65 mA ±25 ±50 mVpk
Load transient response VBAT = 3.6 V, IO = 5 to 65 mA, pulse of 10 µs, tr = tf = 0.1 µs 50 mVpk
IDD (idle) Power supply current from VBAT to DC-DC, enabled, unloaded IO = 0 mA 30 50 µA
IDD (disabled) Power supply current from VBAT, DC-DC Disabled, Unloaded VBAT = 2.3 V to 5.5 V, IO = 0 mA, CT_CP_HPD Low 2 µA
IDD(system off) Power supply current from VBAT, VCCA =0 V VCCA = 0 V 5 µA
I_inrush (startup) Inrush current, average over T_startup time VBAT = 2.3 V to 5.5 V, IO = 65 mA 100 mA
TSD Thermal shutdown Increasing junction temperature 140 °C
ΔTSD Thermal shutdown hysteresis Decreasing junction temperature 20 °C
ISC Short-circuit current limit from output 5-Ω short to GND 500 mA

6.8 Electrical Characteristics: Passive Components

PARAMETER TYP UNIT
LIN External inductor, 0805 footprint 1 µH
CIN Input capacitor, 0603 footprint 4.7 µF
COUT Output capacitor, 0603 footprint 4.7 µF
CVCCA Input capacitor, 0402 footprint 0.1 µF

6.9 Electrical Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A/x_B Ports)

TA = –40°C to 85°C unless otherwise specified
PARAMETER TEST CONDITIONS VCCA MIN TYP MAX UNIT
VOHA IOH = –10 μA, VI = VIH 1.1 V to 3.6 V VCCA × 0.8 V
VOLA IOL = 10 μA, VI = VIL 1.1 V to 3.6 V VCCA × 0.17 V
VOHB IOH = –10 μA, VI = VIH 5VOUT × 0.9 V
VOLB IOL = 3 mA, VI = VIL 0.4 V
ΔVT hysteresis SDx_A (VT+ – VT–) 1.1 V to 3.6 V 40 mV
SDx_B (VT+ – VT–) 1.1 V to 3.6 V 400
RPU (Internal pullup) SCL_A, SDA_A, Internal pullup connected to VCCA rail 10 kΩ
SCL_B, SDA_B, Internal pullup connected to 5-V rail 1.75
IPULLUPAC Transient boosted pullup current (rise time accelerator) SCL_B, SDA_B, Internal pullup connected to 5-V rail 15 mA
IOFF A port VCCA = 0 V, VI or VO = 0 to 3.6 V 0 V ±5 µA
B port 5VOUT = 0 V, VI or VO = 0 to 5.5 V 0 V to 3.6 V ±5
IOZ B port VO = VCCO or GND 1.1 V to 3.6 V ±5 µA
A port VI = VCCI or GND 1.1 V to 3.6 V ±5

6.10 Electrical Characteristics: Voltage Level Shifter: CEC Lines (x_A/x_B Ports)

TA = –40°C to 85°C unless otherwise specified
PARAMETER TEST CONDITIONS VCCA MIN TYP MAX UNIT
VOHA IOH = –10 µA, VI = VIH 1.1 V to 3.6 V VCCA × 0.8 V
VOLA IOL = 10 µA, VI = VIL 1.1 V to 3.6 V VCCA × 0.17 V
VOHB IOH = –10 µA, VI = VIH 3.3V (internal) × 0.9(1) V
VOLB IOL = 3 mA, VI = VIL 0.4 V
ΔVT hysteresis CEC_A (VT+ – VT–) 1.1 V to 3.6 V 40 mV
CEC_B (VT+ – VT–) 1.1 V to 3.6 V 300
RPU (Internal pullup) CEC_A Internal pullup connected to VCCA rail 10 kΩ
CEC_B Internal pullup connected to internal 3.3-V rail 26
IOFF A port VCCA = 0 V, VI or VO = 0 to 3.6 V 0 V ±5 µA
B port 5VOUT = 0 V, VI or VO = 0 to 5.5 V 0 V to 3.6 V ±1.8
IOZ B port VO = VCCO or GND 1.1 V to 3.6 V ±5 µA
A port VI = VCCI or GND 1.1 V to 3.6 V ±5
(1) 3.3 V (internal) is an internally generated voltage node for the CEC_B output buffer supply reference. An LDO generates this 3.3 V from 5VOUT when LS_OE = H & CT_CP_HPD = H

6.11 Electrical Characteristics: Voltage Level Shifter: HPD Line (x_A/x_B Ports)

TA = –40°C to 85°C unless otherwise specified
PARAMETER TEST CONDITIONS VCCA MIN TYP MAX UNIT
VOHA IOH = –3 mA, VI = VIH 1.1 V to 3.6 V VCCA × 0.7 V
VOLA IOL = 3 mA, VI = VIL 1.1 V to 3.6 V 0.4 V
ΔVT hysteresis HPD_B (VT+ – VT–) 1.1 V to 3.6 V 200 mV
RPD (Internal pulldown) HPD_B, Internal pulldown connected to GND 11 kΩ
IOZ A port VI = VCCI or GND 3.6 V ±5 µA

6.12 Electrical Characteristics: LS_OE, CT_CP_HPD

TA = –40°C to 85°C unless otherwise specified
PARAMETER TEST CONDITIONS VCCA MIN TYP MAX UNIT
II VI = VCCA or GND 1.1 V to 3.6 V ±12 µA

6.13 Electrical Characteristics: I/O Capacitance

TA = –40°C to 85°C unless otherwise specified
PARAMETER TEST CONDITIONS VCCA MIN TYP MAX UNIT
CI Control inputs VI = 1.89 V or GND, AC input = 30 mV(p-p); f = 10 MHz 1.1 V to 3.6 V 7.1 pF
CIO A port VO = 1.89 V or GND, AC input = 30 mV(p-p); f = 10 MHz, CT_CP_HPD = H, LS_OE = L 1.1 V to 3.6 V 8.3 pF
B port VO = 5 V or GND, AC input = 30 mV(p-p); f = 10 MHz, CT_CP_HPD = H, LS_OE = L 3.3 V 15 pF
CIO SCL_B, SDA_B VBAT = 0 V, Vbias = 2.5 V; AC input = 3.5 V(p-p); f = 100 kHz 0 V 20 pF
CEC_B VBAT = 0 V, Vbias = 1.65 V; AC input = 2.5 V(p-p); f = 100 kHz 0 V 20 pF
VBAT = 3.3 V, Vbias = 1.65 V; AC input = 2.5 V(p-p); f = 100 kHz, CT_CP_HPD = H, LS_OE = L 3.3 V 20 pF

6.14 Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CL Bus load capacitance (B side) 750 pF
Bus load capacitance (A side) 15

6.15 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.2 V

VCCA = 1.2 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPHL Propagation delay A to B DDC Channels Enabled 344 ns
B to A 355
tPLH Propagation delay A to B DDC Channels Enabled 452 ns
B to A 178
tf A port fall time A Port DDC Channels Enabled 138 ns
B port fall time B Port 83
tr A port rise time A Port DDC Channels Enabled 194 ns
B port rise time B Port 92
fMAX Maximum switching frequency DDC Channels Enabled 400 kHz

6.16 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.2 V

VCCA = 1.2 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay A to B CEC Channels Enabled 445 ns
B to A 337
tPLH A to B 13 µs
B to A 0.266
tf A port fall time A Port CEC Channels Enabled 140 ns
B port fall time B Port 96
tr A port rise time A Port CEC Channels Enabled 202 ns
B port rise time B Port 15 µs

6.17 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.2 V

VCCA = 1.2 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay B to A CEC Channels Enabled 10 µs
tPLH B to A 9
tf A port fall time A Port CEC Channels Enabled 0.67 ns
tr A port rise time A Port CEC Channels Enabled 0.74 ns

6.18 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.5 V

VCCA = 1.5 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay A to B DDC Channels Enabled 335 ns
B to A 265
tPLH A to B 438
B to A 169
tf A port fall time A Port DDC Channels Enabled 110 ns
B port fall time B Port 83
tr A port rise time A Port DDC Channels Enabled 190 ns
B port rise time B Port 92
fMAX Maximum switching frequency DDC Channels Enabled 400 kHz

6.19 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.5 V

VCCA = 1.5 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay A to B CEC Channels Enabled 437 ns
B to A 267
tPLH A to B 13 µs
B to A 0.264
tf A port fall time A Port CEC Channels Enabled 110 ns
B port fall time B Port 96
tr A port rise time A Port CEC Channels Enabled 202 ns
B port rise time B Port 15 µs

6.20 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.5 V

VCCA = 1.5 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay B to A CEC Channels Enabled 10 µs
tPLH B to A 9
tf A port fall time A Port CEC Channels Enabled 0.47 ns
tr A port rise time A Port CEC Channels Enabled 0.51 ns

6.21 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.8 V

VCCA = 1.8 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay A to B DDC Channels Enabled 334 ns
B to A 229
tPLH A to B 431
B to A 169
tf A port fall time A Port DDC Channels Enabled 94 ns
B port fall time B Port 83
tr A port rise time A Port DDC Channels Enabled 191 ns
B port rise time B Port 92
fMAX Maximum switching frequency DDC Channels Enabled 400 kHz

6.22 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.8 V

VCCA = 1.8 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay A to B CEC Channels Enabled 441 ns
B to A 231
tPLH A to B 13 µs
B to A 0.26
tf A port fall time A Port CEC Channels Enabled 94 ns
B port fall time B Port 96
tr A port rise time A Port CEC Channels Enabled 201 ns
B port rise time B Port 15 µs

6.23 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.8 V

VCCA = 1.8 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay B to A CEC Channels Enabled 10 µs
tPLH B to A 9
tf A port fall time A Port CEC Channels Enabled 0.41 ns
tr A port rise time A Port CEC Channels Enabled 0.45 ns

6.24 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 2.5 V

VCCA = 2.5 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay A to B DDC Channels Enabled 330 ns
B to A 182
tPLH A to B 423
B to A 166
tf A port fall time A Port DDC Channels Enabled 79 ns
B port fall time B Port 83
tr A port rise time A Port DDC Channels Enabled 188 ns
B port rise time B Port 92
fMAX Maximum switching frequency DDC Channels Enabled 400 kHz

6.25 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 2.5 V

VCCA = 2.5 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay A to B CEC Channels Enabled 454 ns
B to A 184
tPLH A to B 13 µs
B to A 0.255
tf A port fall time A Port CEC Channels Enabled 79 ns
B port fall time B Port 96
tr A port rise time A Port CEC Channels Enabled 194 ns
B port rise time B Port 15 µs

6.26 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 2.5 V

VCCA = 2.5 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay B to A CEC Channels Enabled 10 µs
tPLH B to A 9
tf A port fall time A Port CEC Channels Enabled 0.37 ns
tr A port rise time A Port CEC Channels Enabled 0.39 ns

6.27 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 3.3 V

VCCA = 3.3 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay A to B DDC channels enabled 323 ns
B to A 158
tPLH A to B 421
B to A 162
tf A port fall time A Port DDC channels enabled 71 ns
B port fall time B Port 84
tr A port rise time A Port DDC channels enabled 188 ns
B port rise time B Port 92
fMAX Maximum switching frequency DDC channels enabled 400 kHz

6.28 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 3.3 V

VCCA = 3.3 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay A to B CEC channels enabled 450 ns
B to A 160
tPLH A to B 13 µs
B to A 0.251
tf A port fall time A Port CEC channels enabled 71 ns
B port fall time B Port 96
tr A port rise time A Port CEC channels enabled 194 ns
B port rise time B Port 15 µs

6.29 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 3.3 V

VCCA = 3.3 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay B to A CEC channels enabled 10 µs
tPLH B to A 9
tf A port fall time A Port CEC channels enabled 0.35 ns
tr A port rise time A Port CEC channels enabled 0.37 ns

6.30 Typical Characteristics

TPD12S015A g_loadtransresp_llse19.gif
Figure 1. Load Transient Response
TPD12S015A g_tstart_llse19.gif
Figure 3. tSTART
TPD12S015A g_ieclamp_8kv_llse19.gif
Figure 5. IEC Clamping Waveforms 8-kV Contact
(IEC ESD Pins)
TPD12S015A g_xtalk_llse19.gif
Figure 7. Channel-to-Channel Crosstalk
TPD12S015A C001_SLVSBM6.png
Figure 9. Power Derating Curve
TPD12S015A g_eye1_02_llse74.gif
Figure 11. Eye Diagram Performance on a Test Board for the D+, D- Lines at 2.5 Gbps
TPD12S015A g_eye2_02_llse74.gif Figure 13. Eye Diagram Performance on a Test Board for the D+, D- Lines at 3.3 Gbps
TPD12S015A g_linetransresp_llse19.gif
Figure 2. Line Transient Response
TPD12S015A g_dcstartsd_llse19.gif
Figure 4. DC-DC Start-Up and Shutdown
TPD12S015A g_ieclamp_neg8kv_llse19.gif
Figure 6. IEC Clamping Waveforms -8 kV Contact (IEC ESD Pins)
TPD12S015A g_insertloss_llse19.gif
Figure 8. Insertion Loss Data Line to GND
TPD12S015A g_eye1_01_llse74.gif
Figure 10. Eye Diagram Performance on a Test Board for the D+, D- Lines at 2.5 Gbps
TPD12S015A g_eye2_01_llse74.gif
Figure 12. Eye Diagram Performance on a Test Board for the D+, D- Lines at 3.3 Gbps

7 Parameter Measurement Information

TPD12S015A pmi1_llse19.gif
PIN CL
DDC, CEC (A side) 750 pF
DDC, CEC, HPD (B side) 15 pF
TPD12S015A pmi2_llse19.gif
A. RT termination resistance must be equal to ZOUT of pulse generators.
B. CL includes probe and jig capacitance.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 14. Test Circuit and Voltage Waveforms

 
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