TPD2S300 USB Type C Short-to-VBUS and IEC ESD Protector for the CC Pins

1 Features

2 Channels of Short-to-V_BUS Overvoltage Protection (CC1, CC2): 24-V_DC Tolerant
2 Channels of IEC 61000-4-2 ESD Protection (CC1, CC2)
Low quiescent current: 3.23 µA (Typical), V_PWR, V_M = 3.3 V
CC1, CC2 Overvoltage Protection FETs 200 mA capable for passing V_CONN power
CC Dead Battery Resistors Integrated for handling dead battery use case in mobile devices
1.4-mm × 1.4-mm WCSP Package

2 Applications

Smartphones
Laptop PC
Tablets
Wall Adaptors
Power Banks
Power Drills

3 Description

The TPD2S300 is a single chip USB Type-C port protection solution that provides 20-V Short-to-V_BUS overvoltage and IEC ESD protection for the CC1 and CC2 pins.

Since the release of the USB Type-C connector, many products and accessories for USB Type-C have been released which do not meet the USB Type-C specification. One example of this is USB Type-C Power Delivery adaptors that start out with 20 V on the V_BUS line. Another concern for USB Type-C is that mechanical twisting and sliding of the connector could short pins due to the close proximity they have in this small connector. This can cause 20-V V_BUS to be shorted to the CC pins. Also, due to the close proximity of the pins in the Type-C connector, there is a heightened concern that debris and moisture is going to cause the 20-V V_BUS pin to be shorted to the CC pins.

These non-ideal equipments and mechanical events make it necessary for the CC pins to be 20-V tolerant, even though they only operate at 5 V or lower. The TPD2S300 enables the CC pins to be 20-V tolerant without interfering with normal operation by providing overvoltage protection on the CC pins. The device places high voltage FETs in series on the CC lines. When a voltage above the OVP threshold is detected on these lines, the high voltage switches are opened up, isolating the rest of the system from the high voltage condition present on the connector.

Finally, most systems require IEC61000-4-2 system level ESD protection for their external pins. The TPD2S300 integrates IEC 61000-4-2 ESD protection for the CC1 and CC2 pins, removing the need to place high voltage TVS diodes externally on the connector.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPD2S300	WCSP (9)	1.40 mm × 1.40 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Application Diagram

4 Revision History

DATE	REVISION	NOTES
April 2017	*	Initial release.

5 Pin Configuration and Functions

YFF Package

9-Pin WCSP

Top Side Marking View

YFF Package

9-Pin WCSP

Bottom, Bump View

Pin Functions

PIN		TYPE	DESCRIPTION
NO.	NAME	TYPE	DESCRIPTION
A1	C_CC1	I/O	Connector side of the CC1 OVP FET. Connect to either CC pin of the USB Type-C connector
A2	VBIAS	Power	Pin for ESD support capacitor. Place a 0.1-µF capacitor on this pin to ground
A3	C_CC2	I/O	Connector side of the CC2 OVP FET. Connect to either CC pin of the USB Type-C connector
B1	CC1	I/O	System side of the CC1 OVP FET. Connect to either CC pin of the CC/PD controller
B2	GND	GND	Ground
B3	CC2	I/O	System side of the CC2 OVP FET. Connect to either CC pin of the CC/PD controller
C1	FLT	O	Open drain for fault reporting
C2	VPWR	Power	2.7 V–4.5 V power supply
C3	VM	I	Voltage mode pin. Place 2.7 V–4.5 V on pin to operate for CC, PD, and FRS. Place 8.7 V–22 V on pin to operate the device in low resistance mode as well

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_I	Input voltage	V_PWR	–0.3	5.5	V
V_I	Input voltage	VM	–0.3	28	V
V_O	Output voltage	FLT	–0.3	6	V
V_O	Output voltage	VBIAS	–0.3	24	V
V_IO	I/O voltage	CC1, CC2	–0.3	6	V
V_IO	I/O voltage	C_CC1, C_CC2	–0.3	24	V
T_A	Operating free air temperature		–40	85	°C
T_J	Operating junction temperature		–40	105	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings—JEDEC Specification

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾		±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

6.3 ESD Ratings—IEC Specification

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	IEC 61000-4-2, C_CC1, C_CC2	Contact discharge	±8000	V
V_(ESD)	Electrostatic discharge	IEC 61000-4-2, C_CC1, C_CC2	Air-gap discharge	±15000	V

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_I	Input voltage	V_PWR	2.7	3.3	4.5	V
V_I	Input voltage	VM	2.7		22	V
V_O	Output voltage	FLT Pull-up resistor power rail	2.7		5.5	V
V_IO	I/O voltage	CC1, CC2, C_CC1, C_CC2	0		5.5	V
I_VCONN	V_CONN current	Current flowing from CCx to C_CCx			200	mA
	External components⁽¹⁾	FLT Pull-up resistance	1.7		300	kΩ
		VBIAS capacitance⁽²⁾		0.1		µF
		V_PWR capacitance, V_M capacitance	0.3	1		µF

(1) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin. Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature variation. The effective value presented must be within the minimum and maximums listed in the table.

(2) The VBIAS pin requires a minimum 35-V_DC rated capacitor. A 50-V_DC rated capacitor is recommended to reduce capacitance derating. See the VBIAS Capacitor Selection section for more details on VBIAS capacitor selection.

6.5 Thermal Information

THERMAL METRIC⁽¹⁾		TPD2S300	UNIT
		YFF (WCSP)
		9 PINS
R_θJA	Junction-to-ambient thermal resistance	107.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	0.9	°C/W
R_θJB	Junction-to-board thermal resistance	28.1	°C/W
ψ_JT	Junction-to-top characterization parameter	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	28.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
CC OVP SWITCHES
R_{ON_VCONN_1}	On resistance of CC OVP FETs VCONN operation	VM = 8.7 V, CCx = 3 V, I_CCx = 0.6 A, –40°C ≤ T_J ≤ 105°C			0.560	Ω
R_{ON_VCONN_2}	On resistance of CC OVP FETs VCONN operation	VM = 8.7 V, CCx = 4.87 V, I_CCx = 0.2 A, –40°C ≤ T_J ≤ 105°C			0.608	Ω
R_{ON_FRS}	On resistance of CC OVP FETs fast role swap operation	VM = 2.7 V, CCx = 0.49 V, I_CCx = 30 mA, –40°C ≤ T_J ≤ 105°C			1.3	Ω
R_{ON_CC_ANA}	On resistance of CC OVP FETs CC analog operation	VM = 2.7 V, CCx = 2.45 V, I_CCx = 400 µA, –40°C ≤ T_J ≤ 105°C			18.7	Ω
R_{ON_PD}	On resistance of CC OVP FETs CC USB-PD operation	VM = 2.7 V, CCx = 1.2 V, I_CCx = 250 µA, –20°C ≤ T_J ≤ 105°C			13	Ω
R_{ONFLAT_VCONN_1}	On resistance flatness of CC OVP FETs VCONN operation	VM = 8.7 V, sweep CCx from 0 V to 5.5 V, measure the difference in resistance. I_CCx = 0.2 A, –40°C ≤ T_J ≤ 105°C			0.2	Ω
C_{ON_CC}	Equivalent on capacitance for CC pins	Capacitance from C_CCx or CCx to GND when device is powered. V_{C_CCx}/V_CCx = 0 V to 1.2 V, f = 400 kHz, –40°C ≤ T_J ≤ 105°C	30		120	pF
VTH_DB	Threshold voltage of the pull-down FET in series with RD during dead battery	I_C_CCx = 80 uA	0.5	0.9	1.2	V
R_D	Dead battery pull-down resistance (only present when device is unpowered). Effective resistance of R_D and FET in series	V_PWR = 0 V, V_{C_CCx} = 2.6 V	4.1	5.1	6.1	kΩ
V_{OVPCC_RISE}	Rising overvoltage protection threshold on C_CCx pins	Place 5.5 V on C_CCx pins. Step up voltage until the FLT pin is asserted .–20°C ≤ T_J ≤ 105°C	5.55		6.18	V
V_{OVPCC_HYS}	OVP threshold hysteresis	Place 6.5 V on C_CCx. Step down the voltage on C_CCx until the FLT pin is deasserted. Measure the difference between rising and falling OVP thresholds		50		mV
BW_ON	On bandwidth single ended (–3dB)	Measure the –3-dB bandwidth from C_CCx to CCx. Single ended measurement, 50-Ω system. Vcm = 0 V to 1.2 V		80		MHz
V_{STBUS_CC}	Short-to-VBUS tolerance on the C_CCx pins	Hot-Plug C_CCx with a 1 meter USB Type C Cable. Place a 30-Ω load on CCx			24	V
V_{STBUS_CC_CLAMP}	Short-to-VBUS system-side clamping voltage on the CCx pins	Hot-Plug C_CCx with a 1-meter USB Type C Cable. Hot-plug voltage C_CCx = 2 4V. VPWR = 3.3 V. Place a 30-Ω load on CCx		8		V
POWER SUPPLY AND LEAKAGE CURRENTS
V_{PWR_UVLO}	V_PWR undervoltage lockout threshold	Place 1 V on VPWR and raise the voltage until the CC FETs turn ON	1.9	2.3	2.55	V
V_{PWR_UVLO_HYS}	V_PWR UVLO hysteresis	Place 3 V on VPWR and lower the voltage until the CC FETs turn off. Calculate the difference between the rising and falling UVLO threshold	50	100	200	mV
I_{VPWR_1S}	VPWR quiescent current for 1S battery	VPWR = 3.3 V, VM = 3.3 V, C_CCx = 3.6 V, –40°C ≤ T_J ≤ 105°C		3.23	7	µA
I_{VM_1S}	VM quiescent current for 1S battery	VPWR = 3.3 V, VM = 3.3 V, C_CCx = 3.6 V, –40°C ≤ T_J ≤ 105°C			1	µA
I_{VPWR_1S_Max}	VPWR quiescent current for 1S battery max	VPWR = 4.5 V, VM = 4.5 V, C_CCx = 3.6 V, –40°C ≤ T_J ≤ 105°C			12	µA
I_{VM_1S_Max}	VM quiescent current for 1S battery max	VPWR = 4.5 V, VM = 4.5 V, C_CCx = 3.6 V, –40°C ≤ T_J ≤ 105°C			1	µA
I_{VPWR_3S}	VPWR quiescent current for 3S battery	VPWR = 3.6 V, VM = 13.5 V, C_CCx = 3.6 V, –40°C ≤ T_J ≤ 105°C			8	µA
I_{VM_3S}	VM quiescent current for 3S battery	VPWR = 3.6 V, VM = 13.5 V, C_CCx = 3.6 V, –40°C ≤ T_J ≤ 105°C			3.5	µA
I_{VPWR_4S}	VPWR quiescent current for 4S battery	VPWR = 3.6 V, VM = 18 V, C_CCx = 3.6 V, –40°C ≤ T_J ≤ 105°C			8	µA
I_{VM_4S}	VM quiescent current for 4S battery	VPWR = 3.6 V, VM = 18 V, C_CCx = 3.6 V, –40°C ≤ T_J ≤ 105°C			4.5	µA
I_{CC_LEAK}	Leakage current for CC pins when device is powered	VPWR = 3.3 V, VM = 3.3 V, VC_CCx = 3.6 V, CCx pins are floating, measure leakage into C_CCx pins. Result must be same if CCx side is biased and C_CCx is left floating			5	µA
I_{C_CC_LEAK_OVP}	Leakage current for C_CCx pins when device is in OVP	VPWR = VM = 0 V or 3.3 V, VC_CCx = 24 V, CCx = 0 V, measure leakage into C_CCx pins			1500	µA
I_{CC_LEAK_OVP}	Leakage current for CCx pins when device is in OVP	VPWR = VM = 0 V or 3.3 V, VC_CCx = 24 V, CCx = 0 V, measure leakage flowing out of CCx pins			40	µA
FLT PIN
V_OL	Low-level output voltage for FLT pin	IOL = 3 mA. Measure the voltage at the FLT pin			0.4	V

6.7 Timing Requirements

		MIN	NOM	MAX	UNIT
POWER-ON AND POWER-OFF TIMINGS
t_ON	Time from crossing rising VPWR UVLO until CC OVP FETs are on. VPWR slew rate = 0.347 V/µs			200	µs
dV_{PWR_OFF}/dt	Minimum slew rate allowed to guarantee CC FETs turn off during a power off	–0.5			V/µs
OVERVOLTAGE PROTECTION
t_{OVP_RESPONSE_CC}	OVP response time on the CC pins. Time from OVP asserted until OVP FETs turn off. Hot-Plug C_CCx to 24 V with a 1-m cable. C_CCx slew rate = 4 V/ns. Place a 30-Ω on CCx		145		ns
t_{OVP_RECOVERY_CC}	OVP recovery time on the CC pins. Time from OVP removal until FET turns back on.VM = 10.8 V. Step C_CCx down from 6.3 V to 3.3 V at a 0.343-V/µs slew rate		30		µs
t_{OVP_RECOVERY_CC}	OVP recovery time on the CC pins. Time from OVP removal until FET turns back on.VM = 3.3 V. Step C_CCx down from 6.3 V to 0.49 V at a 0.321-V/µs slew rate		200		µs
t_{OVP_FLT_ASSERTION}	Time from OVP asserted to FLT assertion.FLT assertion is when the FLT pin reaches 10% of its starting value. C_CCx from 0 V to 6.3 V at a 0.645-V/µs slew rate		1		µs
t_{OVP_FLT_DEASSERTION}	Time from OVP removal to FLT deassertion. FLT deassertion is when the FLT pin reaches 90% of its final value. C_CCx from 6.3 V to 0 V at a 0.696-V/µs slew rate		20		µs