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  • TPS23882 Type-3 2-Pair 8-Channel PoE 2 PSE Controller with SRAM and 200 mΩ RSENSE

    • SLVSF21D August   2019  – August 2020 TPS23882

      PRODUCTION DATA  

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  • TPS23882 Type-3 2-Pair 8-Channel PoE 2 PSE Controller with SRAM and 200 mΩ RSENSE
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Detailed Pin Description
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Semiauto
        3. 9.1.1.3 Manual/Diagnostic
        4. 9.1.1.4 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 PoE 2 Type-3 2-Pair PoE
      4. 9.1.4 Requested Class versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Classification
      3. 9.4.3 DC Disconnect
      4.      41
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
        2. 9.6.2.2  INTERRUPT MASK Register
        3. 9.6.2.3  POWER EVENT Register
        4. 9.6.2.4  DETECTION EVENT Register
        5. 9.6.2.5  FAULT EVENT Register
        6. 9.6.2.6  START/ILIM EVENT Register
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 9.6.2.12 POWER STATUS Register
        13. 9.6.2.13 PIN STATUS Register
        14. 9.6.2.14 OPERATING MODE Register
        15. 9.6.2.15 DISCONNECT ENABLE Register
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 9.6.2.18 TIMING CONFIGURATION Register
        19. 9.6.2.19 GENERAL MASK Register
        20. 9.6.2.20 DETECT/CLASS RESTART Register
        21. 9.6.2.21 POWER ENABLE Register
        22. 9.6.2.22 RESET Register
        23. 9.6.2.23 ID Register
        24. 9.6.2.24 Connection Check and Auto Class Status Register
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
        30. 9.6.2.30 Power-on Fault Register
        31. 9.6.2.31 PORT RE-MAPPING Register
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
        34. 9.6.2.34 Port Power Allocation Register
        35. 9.6.2.35 TEMPERATURE Register
        36. 9.6.2.36 INPUT VOLTAGE Register
        37. 9.6.2.37 CHANNEL 1 CURRENT Register
        38. 9.6.2.38 CHANNEL 2 CURRENT Register
        39. 9.6.2.39 CHANNEL 3 CURRENT Register
        40. 9.6.2.40 CHANNEL 4 CURRENT Register
        41. 9.6.2.41 CHANNEL 1 VOLTAGE Register
        42. 9.6.2.42 CHANNEL 2 VOLTAGE Register
        43. 9.6.2.43 CHANNEL 3 VOLTAGE Register
        44. 9.6.2.44 CHANNEL 4 VOLTAGE Register
        45. 9.6.2.45 2x FOLDBACK SELECTION Register
        46.       93
        47. 9.6.2.46 FIRMWARE REVISION Register
        48. 9.6.2.47 I2C WATCHDOG Register
        49. 9.6.2.48 DEVICE ID Register
        50. 9.6.2.49 CHANNEL 1 DETECT RESISTANCE Register
        51. 9.6.2.50 CHANNEL 2 DETECT RESISTANCE Register
        52. 9.6.2.51 CHANNEL 3 DETECT RESISTANCE Register
        53. 9.6.2.52 CHANNEL 4 DETECT RESISTANCE Register
        54. 9.6.2.53 CHANNEL 1 DETECT CAPACITANCE Register
        55. 9.6.2.54 CHANNEL 2 DETECT CAPACITANCE Register
        56. 9.6.2.55 CHANNEL 3 DETECT CAPACITANCE Register
        57. 9.6.2.56 CHANNEL 4 DETECT CAPACITANCE Register
        58. 9.6.2.57 CHANNEL 1 ASSIGNED CLASS Register
        59. 9.6.2.58 CHANNEL 2 ASSIGNED CLASS Register
        60. 9.6.2.59 CHANNEL 3 ASSIGNED CLASS Register
        61. 9.6.2.60 CHANNEL 4 ASSIGNED CLASS Register
        62. 9.6.2.61 AUTO CLASS CONTROL Register
        63. 9.6.2.62 CHANNEL 1 AUTO CLASS POWER Register
        64. 9.6.2.63 CHANNEL 2 AUTO CLASS POWER Register
        65. 9.6.2.64 CHANNEL 3 AUTO CLASS POWER Register
        66. 9.6.2.65 CHANNEL 4 AUTO CLASS POWER Register
        67. 9.6.2.66 ALTERNATIVE FOLDBACK Register
        68. 9.6.2.67 SRAM CONTROL Register
          1. 9.6.2.67.1 SRAM START ADDRESS (LSB) Register
          2. 9.6.2.67.2 SRAM START ADDRESS (MSB) Register
          3. 9.6.2.67.3 118
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Introduction to PoE
        1. 10.1.1.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not shown in the schematic diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
  15. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RTQ|56
    • MPQF168D
Thermal pad, mechanical data (Package|Pins)
  • RTQ|56
    • QFND490A
Orderable Information
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  • slvsf21d_pm
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DATA SHEET

TPS23882 Type-3 2-Pair 8-Channel PoE 2 PSE Controller with SRAM and 200 mΩ RSENSE

1 Features

  • IEEE 802.3bt PSE solution for PoE 2 Type-3 2-Pair Power Over Ethernet applications
  • Compatible with TI's FirmPSE system firmware
  • SRAM Programmable memory
  • Programmable power limiting accuracy ±3%
  • 200-mΩ Current sense resistor
  • Legacy PD capacitance measurement
  • Selectable 2-pair port power allocations
    • 4 W, 7 W, 15.4 W, or 30 W
  • Dedicated 14-bit integrating current ADC per port
    • Noise immune MPS for DC disconnect
    • 2% Current sensing accuracy
  • 1- or 3-Bit fast port shutdown input
  • Auto-class discovery and power measurement
  • Never Fooled 4-Point detection
  • Inrush and operational foldback protection
  • 425-mA and 1.25-A Selectable current limits
  • Port re-mapping
  • 8-Bit or 16-bit I2C communication
  • Flexible processor controlled operating modes
    • Auto, semi auto and manual / diagnostic
  • Per Port voltage monitoring and telemetry
  • –40°C to +125°C Temperature operation

2 Applications

  • Video recorder (NVR, DVR, and so forth)
  • Small business switch
  • Campus and branch switches

3 Description

The TPS23882 is an 8-channel power sourcing equipment (PSE) controller engineered to insert power onto Ethernet cables in accordance with the IEEE 802.3bt standard. The PSE controller can detect powered devices (PDs) that have a valid signature, complete mutual identification, and apply power.

The TPS23882 improves on the TPS2388 with reduced current sense resistors, SRAM programmability, programmable power limiting, capacitance measurement, and compatibility with TI's FirmPSE system firmware (see Device Comparison Table).

Programmable SRAM enables in-field firmware upgradability over I2C to ensure IEEE compliance and interoperability with the latest PoE enabled devices. Dedicated per port ADCs provide continuous port current monitoring and the ability to perform parallel classification measurements for faster port turn on times. A 1.25-A port current limit and adjustable power limiting allows for the support of non-standard applications above 60-W sourced. The 200-mΩ current sense resistor and external FET architecture allow designs to balance size, efficiency, thermal and solution cost requirements. 

Port remapping and pin-to-pin compatibility with the TPS2388, TPS23880, and TPS23881 devices eases migration from previous generation PSE designs and enables interchangeable 2-layer PCB designs to accommodate different system PoE power configurations.

Device Information(1)
PART NUMBERPACKAGEBODY SIZE (NOM)
TPS23882VQFN (56)8.00 mm × 8.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-85A18196-4E2D-4658-B4E8-DEC1C776C070-low.gif Simplified Schematic

4 Revision History

Changes from Revision C (May 2020) to Revision D (August 2020)

  • Updated the numbering format for tables, figures and cross-references throughout the documentGo

Changes from Revision B (October 2019) to Revision C (May 2020)

  • Deleted Autonomous operation description throughout data sheet for clarification Go
  • Changed Gate 1-8 MAX voltage from 12 to 13 V in the Section 7.1 table Go

Changes from Revision A (September 2019) to Revision B (December 2019)

  • Fixed typo in device number on first page Go

Changes from Revision * (August 2019) to Revision A (September 2019)

  • Changed from Advance Information to Production Data Go
  • First Public ReleaseGo

5 Device Comparison Table

Table 5-1 summarizes the primary differences between the available 2-Pair PSE devices.

KEY FEATURES TPS23880 TPS23881 TPS23882
Compatible with TI's FirmPSE system firmware N/A Yes Yes
Pin to Pin compatible Yes Yes Yes
Number of PSE Channels 8 8 8
Supported IEEE 802.3 PSE Types PoE 2
802.3bt Type 3 or 4
(2 or 4 Pair)		 PoE 2
802.3bt Type 3 or 4
(2 or 4 Pair)		 PoE 2
802.3bt Type 3 (2-Pair)
RSENSE 0.255 Ω 0.200 Ω 0.200 Ω
2-Pair PCUT programable ranges 0.5 W to 54 W 2 W to 65 W 2 W to 65 W
4-Pair PCUT programable ranges 0.5 W to 108 W 4 W to 127 W N/A
90+ W 4-pair PCUT accuracy ±3.0 % ±2.5 % N/A
Channel capacitance measurement range N/A 1 µF to 12 µF 1 µF to 12 µF
ULA Packaging No Yes (TPS23881A) N/A
I2C Programmable SRAM Memory 16 kB 16 kB 16 kB
Table 5-1 2-Pair PSE Key Feature Comparisons
KEY FEATURES TPS23861 TPS2388 TPS23881 TPS23882
Compatible with TI's FirmPSE system firmware N/A N/A Yes Yes
Pin to Pin compatible N/A Yes Yes Yes
Number of PSE Channels 4 8 8 8
Supported IEEE 802.3 PSE Types PoE 1
802.3at Type 1 or 2		 PoE 1
802.3at Type 1 or 2		 PoE 2
802.3bt Type 3 or 4
(2 or 4 Pair)		 PoE 2
802.3bt Type 3 (2-Pair)
RSENSE 0.255 Ω 0.255 Ω 0.200 Ω 0.200 Ω
2-Pair PCUT programable ranges N/A
ICUT adjustable up to 920 mA		 N/A
ICUT adjustable up to 920 mA		 2 W to 65 W 2 W to 65 W
TMPS 15 ms 15 ms 3 ms 3 ms
Port Current Limit (1x / 2x) 425 mA / 1060 mA 425 mA / 1060 mA 425 mA / 1250 mA 425 mA / 1250 mA
Channel capacitance measurement range N/A N/A 1 µF to 12 µF 1 µF to 12 µF
PD Autoclass Discovery and Power Measurement N/A N/A Yes Yes
I2C Programmable SRAM Memory N/A N/A 16 kB 16 kB

 
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