TPS31xx Ultralow Supply-Current Voltage Monitor With Optional Watchdog
- SLVS363G August 2001 – September 2016 TPS3103 , TPS3106 , TPS3110
  
  PRODUCTION DATA.

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DATA SHEET

TPS31xx Ultralow Supply-Current Voltage Monitor With Optional Watchdog

1 Features

Precision Supply Voltage Supervision Range:
0.9 V, 1.2 V, 1.5 V, 1.6 V, 2 V, and 3.3 V
High Trip-Point Accuracy: 0.75%
Supply Current of 1.2 μA (Typical)
RESET Defined With Input Voltages as Low as 0.4 V
Power-On Reset Generator With a Delay Time of 130 ms
Push/Pull or Open-Drain RESET Outputs
Package Temperature Range: –40°C to 125°C

2 Applications

Applications Using Low-Power DSPs, Microcontrollers, or Microprocessors
Portable and Battery-Powered Equipment
Intelligent Instruments
Wireless Communication Systems
Industrial Equipment
Notebook and Desktop Computers

Typical Application Schematic

TPS3103 TPS3106 TPS3110 desc_fbd_po-lvs363.gif

3 Description

The TPS310x and TPS311x families of supervisory circuits provide circuit initialization and timing supervision, primarily for DSP and processor-based systems.

During power-on, RESET is asserted low when the supply voltage (V_DD) becomes higher than 0.4 V. Thereafter, the supervisory circuit monitors V_DD and keeps the RESET output low as long as V_DD remains below the threshold voltage (V_IT–). To ensure proper system reset, after V_DD surpasses the threshold voltage, an internal timer delays the transition of the RESET signal from low to high for the specified time. When V_DD drops below V_IT–, the output transitions low again.

All the devices of this family have a fixed-sense threshold voltage (V_IT–) set by an internal voltage divider.

The TPS3103 and TPS3106 devices have an active-low, open-drain RESET output and either an integrated power-fail input (PFI) or SENSE input with corresponding outputs for monitoring other voltages. The TPS3110 has an active-low push/pull RESET and a watchdog timer to monitor the operation of microprocessors. All three devices have a manual reset pin that can be used to force the outputs low regardless of the sensed voltages.

The product spectrum is designed for supply voltages of 0.9 V up to 3.6 V. The circuits are available in 6-pin SOT-23 packages. The TPS31xx family is characterized for operation over a temperature range of –40°C to 125°C.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS3103xxx	SOT-23 (6)	2.90 mm × 1.60 mm
TPS3106xxx
TPS3110xxx

For all available packages, see the orderable addendum at the end of the data sheet.

4 Revision History

Changes from F Revision (November 2015) to G Revision

Changed Package Temperature Range Features bullet to extend to 125°C Go
Changed supply voltage and temperature range in last paragraph of Description section Go
Changed maximum specifications in Supply voltage, All other pins, and Operating temperature parameters in Absolute Maximum Ratings tableGo
Changed maximum specifications in V_DD, PFI, and T_J parameters of Recommended Operating Conditions tableGo
Added T_A = –40°C to 125°C rows to V_IT– parameter of Electrical Characteristics tableGo
Added second row to V_IT–(S) parameter of Electrical Characteristics tableGo
Changed I_DD parameter of Electrical Characteristics tableGo
Changed Typical Characteristics curves TPS3110E09 Supply Current vs Supply Voltage, TPS3110E09 Low-Level Output Voltage vs Low-Level Output Current, TPS3110E09 Low-Level Output Voltage vs Low-Level Output Current, TPS3110E09 High-Level Output Voltage vs High-Level Output Current, and TPS3110K33 High-Level Output Voltage vs High-Level Output Current Go
Changed Normalized Threshold Voltage vs Free-Air Temperature curveGo
Changed supply voltage range in first sentence of Overview section Go
Changed supply voltage range in description of Application Information section Go
Changed Normalized Threshold Voltage vs Free-Air Temperature figureGo
Changed supply voltage range in first sentence of Power Supply Recommendations sectionGo

Changes from E Revision (September 2007) to F Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
Changed title of document Go
Deleted Features bullet for SOT23-6 package Go
Changed front-page figureGo
Changed second paragraph of Description section Go
Changed fourth paragraph of Description sectionGo
Changed Pin Configuration and Functions section; updated table format Go
Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statementGo
Deleted clamp current from Absolute Maximum Ratings table; changed to currentGo
Deleted soldering temperature specification from Absolute Maximum Ratings tableGo
Changed "free-air temperature" to "junction temperature" in Recommended Operating Conditions condition statement Go
Added Thermal Information table; deleted Dissipation Ratings tableGo
Changed "free-air temperature" to "junction temperature" in Electrical Characteristics condition statement Go
Changed Switching Characteristics tableGo
Changed Figure 1 title and timing drawing Go
Changed Figure 2 titleGo
Changed Figure 3Go
Changed Figure 4Go

5 Available Options

DEVICE	RESET OUTPUT	RSTSENSE, RSTVDD OUTPUT	SENSE INPUT	WDI INPUT	PFO OUTPUT
TPS3103	Open-drain				Open-drain
TPS3106		Open-drain	✓
TPS3110	Push-pull		✓	✓

6 Pin Configuration and Functions

TPS3103 DBV Package

6-Pin SOT-23

Top View

TPS3103 TPS3106 TPS3110 tps3103_po-lvs363.gif

TPS3106 DBV Package

6-Pin SOT-23

Top View

TPS3103 TPS3106 TPS3110 tps3106_po-lvs363.gif

TPS3110 DBV Package

6-Pin SOT-23

Top View

TPS3103 TPS3106 TPS3110 tps3110_po-lvs363.gif

Pin Functions

PIN				I/O	DESCRIPTION
NAME	TPS3103	TPS3106	TPS3110	I/O	DESCRIPTION
GND	2	2	2	—	GND
MR	3	3	3	I	Manual-reset input. Pull low to force a reset. RESET remains low as long as MR is low and for the time-out period after MR goes high. Leave unconnected or connect to V_DD when unused.
PFI	4	—	—	I	Power-fail input compares to 0.551 V with no additional delay. Connect to V_DD if not used.
PFO	5	—	—	O	Power-fail output. Goes high when voltage at PFI rises above 0.551 V.
RESET	1	—	1	O	Active-low reset output. Either push-pull or open-drain output stage.
RSTSENSE	—	5	—	O	Active-low reset output. Logic level at RSTSENSE only depends on the voltage at SENSE and the status of MR.
RSTVDD	—	1	—	O	Active-low reset output. Logic level at RSTVDD only depends on the voltage at V_DD and the status of MR.
SENSE	—	4	4	I	A reset is asserted if the voltage at SENSE is lower than 0.551 V. Connect to V_DD if unused.
V_DD	6	6	6	I	Supply voltage. Powers the device and monitors its own voltage.
WDI	—	—	5	I	Watchdog timer input. If WDI remains high or low longer than the time-out period, then reset is triggered. The timer clears when reset is asserted or when WDI sees a rising edge or a falling edge.

7 Specifications

7.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage⁽²⁾	V_DD	–0.3	4	V
MR Pin, RESET (push-pull)	V_MR, V_RESET (push-pull)	–0.3	V_DD + 0.3	V
All other pins⁽²⁾		–0.3	4	V
Maximum low output current	I_OL	–5	5	mA
Maximum high output current	I_OH	–5	5	mA
Input current	I_IK (V_SENSE < 0 V or V_SENSE > V_DD)	–10	10	mA
Output current	I_OK (V_O < 0 V or V_O > V_DD)⁽³⁾	–10	10	mA
Continuous total power dissipation		See Thermal Information
Temperature	Operating, T_J	–40	125	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND. For reliable operation, the device must not be operated at 3.6 V for more than t = 1000h continuously.

(3) Output is clamped for push-pull outputs by the back gate diodes internal to the IC. No clamp exists for the open-drain outputs.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating junction temperature range, unless otherwise noted.

		MIN	MAX	UNIT
V_DD⁽¹⁾	Supply voltage	0.9	3.6	V
V_SENSE	SENSE voltage	0	V_DD	V
WDI	High-level input voltage V_IH at MR	0.7 × V_DD		V
WDI	Low-level input voltage V_IL at MR		0.3 × V_DD	V
WDI	Input transition rise and fall rate at Δt/ΔV at MR		100	ns/V
MR	MR voltage	0	V_DD	V
PFI	PFI voltage	0	3.6	V
T_J	Operating temperature	–40	125	°C

(1) For proper operation of SENSE, PFI, and WDI functions: V_DD ≥ 0.8 V.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS31xx	UNIT
		DBV (SOT-23)
		6 PINS
R_θJA	Junction-to-ambient thermal resistance	183.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	123.3	°C/W
R_θJB	Junction-to-board thermal resistance	29.4	°C/W
ψ_JT	Junction-to-top characterization parameter	20.5	°C/W
ψ_JB	Junction-to-board characterization parameter	29	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating junction temperature range (unless otherwise noted).

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage		V_DD = 3.3 V, I_OH = –3 mA	0.8 × V_DD			V
			V_DD = 1.8 V, I_OH = –2 mA
			V_DD = 1.5 V, I_OH = –1 mA
			V_DD = 0.9 V, I_OH = –0.4 mA
			V_DD = 0.5 V, I_OH = –5 μA	0.7 × V_DD
V_OL	Low-level output voltage		V_DD = 3.3 V, I_OL = 3 mA			0.3	V
			V_DD = 1.5 V, I_OL = 2 mA
			V_DD = 1.2 V, I_OL = 1 mA
			V_DD = 0.9 V, I_OL = 500 μA
V_OL	Low-level output voltage	RESET only	V_DD = 0.4 V, I_OL = 5 μA			0.1	V
V_IT–	Negative-going input threshold voltage⁽¹⁾	TPS31xxE09	T_A = 25°C	0.854	0.86	0.866	V
		TPS31xxE12		1.133	1.142	1.151
		TPS31xxE15		1.423	1.434	1.445
		TPS31xxE16		1.512	1.523	1.534
		TPS31xxH20		1.829	1.843	1.857
		TPS31xxK33		2.919	2.941	2.963
		TPS31xxE09	T_A = –40°C to 125°C	0.817		0.903
		TPS31xxE12		1.084		1.199
		TPS31xxE15		1.362		1.505
		TPS31xxK33		2.823		3.058
V_IT–(S)	Negative-going input threshold voltage⁽¹⁾	SENSE, PFI	V_DD ≥ 0.8 V, T_A = 25°C	0.542	0.551	0.559	V
V_IT–(S)	Negative-going input threshold voltage⁽¹⁾	SENSE, PFI	V_DD ≥ 0.8 V, T_A = –40°C to 125°C	0.5		0.58	V
V_HYS	Hysteresis at V_DD input		0.8 V ≤ V_IT– < 1.5 V		20		mV
			1.6 V ≤ V_IT– < 2.4 V		30
			2.5 V ≤ V_IT– < 3.3 V		50
T_(K)	Temperature coefficient of V_IT−, PFI, SENSE		T_A = –40°C to 85°C		–0.012	–0.019	%/K
V_HYS(S)	Hysteresis at SENSE, PFI input		V_DD ≥ 0.8 V		15		mV
I_IH	High-level input current	MR	MR = V_DD, V_DD = 3.3 V	–25		25	nA
I_IH	High-level input current	SENSE, PFI, WDI	SENSE, PFI, WDI = V_DD, V_DD = 3.3 V	–25		25	nA
I_IL	Low-level input current	MR	MR = 0 V, V_DD = 3.3 V	–47	–33	–25	μA
I_IL	Low-level input current	SENSE, PFI, WDI	SENSE, PFI, WDI = 0 V, V_DD = 3.3 V	–25		25	nA
I_OH	High-level output current at RESET⁽²⁾	Open-drain	V_DD = V_IT– + 0.2 V, V_OH = 3.3 V			200	nA
I_DD	Supply current		T_A = –40°C to 85°C, V_DD > V_IT– (average current), V_DD < 1.8 V		1.2	3	μA
			T_A = –40°C to 125°C, V_DD > V_IT– (average current), V_DD < 1.8 V			3
			T_A = –40°C to 85°C, V_DD > V_IT– (average current), V_DD > 1.8 V		2	4.5
			T_A = –40°C to 125°C, V_DD > V_IT– (average current), V_DD > 1.8 V			5.5
			T_A = –40°C to 85°C, V_DD < V_IT–, V_DD < 1.8 V			22
			T_A = –40°C to 125°C, V_DD < V_IT–, V_DD < 1.8 V			27
			T_A = –40°C to 85°C, V_DD < V_IT–, V_DD > 1.8 V			27
			T_A = –40°C to 125°C, V_DD < V_IT–, V_DD > 1.8 V			32
	Internal pullup resistor at MR			70	100	130	kΩ
C_IN	Input capacitance at MR, SENSE, PFI, WDI		V_IN = 0 V to V_DD		1		pF

(1) To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be placed close to the supply terminals.

(2) Also refers to RSTVDD and RSTSENSE.

7.6 Timing Requirements

At R_L = 1 MΩ, C_L = 50 pF, and T_A = –40°C to 85°C, unless otherwise noted.

				MIN	TYP	MAX	UNIT
t_T(OUT)	Time-out period	at WDI	V_DD ≥ 0.85 V	0.55	1.1	1.65	s
t_W	Pulse duration	at V_DD	V_IH = 1.1 × V_IT–, V_IL = 0.9 × V_IT–, V_IT– = 0.86 V	20			μs
		at MR	V_DD ≥ V_IT– + 0.2 V, V_IL = 0.3 × V_DD, V_IH = 0.7 × V_DD	0.1
		at SENSE	V_DD ≥ V_IT–, V_IH = 1.1 × V_{IT − (S)}, V_IL = 0.9 × V_{IT − (S)}	20
		at PFI	V_DD ≥ 0.85 V, V_IH = 1.1 × V_{IT − (S)},V_IL = 0.9 × V_{IT − (S)}	20
		at WDI	V_DD ≥ V_IT–, V_IL = 0.3 × V_DD, V_IH = 0.7 × V_DD	0.3

7.7 Switching Characteristics

At R_L = 1 MΩ, C_L = 50 pF, and T_A = –40°C to 85°C, unless otherwise noted.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_D	Delay time		V_DD ≥ 1.1 × V_IT–, MR = 0.7 × V_DD. See Timing Requirements.	65	130	195	ms
t_PHL(VDD)	Propagation delay time, high-to-low level output	V_DD to RESET or RSTVDD delay	V_IH = 1.1 × V_IT–, V_IL = 0.9 × V_IT–			40	μs
t_PHL(SENSE)	Propagation delay time, high-to-low level output	SENSE to RESET or RSTSENSE delay	V_DD ≥ 0.8 V, V_IH = 1.1 × V_IT–, V_IL = 0.9 × V_IT–			40	μs
t_PHL(PFO)	Propagation delay time, high-to-low level output	PFI to PFO delay	V_DD ≥ 0.8 V, V_IH = 1.1 × V_IT–, V_IL = 0.9 × V_IT–			40	μs
t_PLH(PFO)	Propagation delay time, low-to-high level output	PFI to PFO delay	V_DD ≥ 0.8 V, V_IH = 1.1 × V_IT–, V_IL = 0.9 × V_IT–			300	μs
t_PHL(MR)	Propagation delay time, high-to-low level output	MR to RESET. RSTVDD, RSTSENSE delay	V_DD ≥ 1.1 × V_IT–, V_IL = 0.3 × V_DD, V_IH = 0.7 × V_DD		1	5	μs

TPS3103 TPS3106 TPS3110 time_3103a-lvs363.gif

Figure 1. RESET Timing Diagram for TPS3103

TPS3103 TPS3106 TPS3110 time_3103b-lvs363.gif

Figure 2. PFO Timing Diagram for TPS3103

TPS3103 TPS3106 TPS3110 time_3106-lvs363.gif

Figure 3. Timing Diagram for TPS3106

TPS3103 TPS3106 TPS3110 time_3110-lvs363.gif

Figure 4. Timing Diagram for TPS3110

7.8 Typical Characteristics

TPS3103 TPS3106 TPS3110 D001_SLVS363.gif

SENSE = V_DD, MR = open, RESET = open, WDI: triggered

Figure 5. TPS3110E09 Supply Current vs Supply Voltage

TPS3103 TPS3106 TPS3110 D003_SLVS363.gif

V_DD = 3.3 V, SENSE = GND, MR = GND, WDI: GND

Figure 7. TPS3110E09 Low-Level Output Voltage vs
Low-Level Output Current

TPS3103 TPS3106 TPS3110 D005_SLVS363.gif

V_DD = 3.3 V, SENSE = V_DD, MR = V_DD, WDI: triggered

Figure 9. TPS3110K33 High-Level Output Voltage vs
High-Level Output Current

TPS3103 TPS3106 TPS3110 D006_SLVS363.gif

Figure 11. Normalized Threshold Voltage vs Free-Air Temperature

TPS3103 TPS3106 TPS3110 D002_SLVS363.gif

V_DD = 0.9 V, SENSE = GND, MR = GND, WDI: GND

Figure 6. TPS3110E09 Low-Level Output Voltage vs
Low-Level Output Current

TPS3103 TPS3106 TPS3110 D004_SLVS363.gif

V_DD = 0.9 V, SENSE = V_DD, MR = V_DD, WDI: triggered

Figure 8. TPS3110E09 High-Level Output Voltage vs
High-Level Output Current

TPS3103 TPS3106 TPS3110 tc_tw_vdd-lvs363.gif

Figure 10. Minimum Pulse Duration at V_DD vs
Threshold Overdrive Voltage

8 Detailed Description

8.1 Overview

The TPS310x and TPS311x families of supervisory circuits operate from supply voltages from 0.9 V to 3.6 V and provide circuit initialization and timing supervision for DSP- and processor-based systems. During power-on, RESET is asserted when the supply voltage (V_DD) exceeds 0.4 V. The devices monitor V_DD and keep the RESET output low as long as V_DD remains below the threshold voltage (V_IT–). To ensure proper system reset, after V_DD surpasses the threshold voltage plus the hysteresis (V_IT– + V_HYS) an internal timer delays the transition of the RESET signal from low to high for the specified time. The delay time starts after V_DD has risen above (V_IT– + V_HYS). When V_DD drops below V_IT–, the output becomes active again.

All the devices of this family have a fixed-V_DD threshold voltage (V_IT–) set by an internal voltage divider. The TPS3103 and TPS3106 devices both have an active-low, open-drain RESET output. The TPS3103 device has an integrated power-fail input (PFI) and corresponding power-fail output (PFO) that can be used for low-battery detection or for monitoring a power supply other than the input supply. The TPS3106 device has a SENSE input with a corresponding output (RSTSENSE) for monitoring voltages other than the input supply. The TPS3110 device has an active-low push/pull RESET and a watchdog timer that is used for monitoring the operation of microprocessors. All three devices have manual reset pin (MR) that can be used to force the outputs low regardless of the sensed voltages.

8.2 Functional Block Diagrams

TPS3103 TPS3106 TPS3110 fbd_3103-lvs363.gif

Figure 12. TPS3103 Functional Block Diagram

TPS3103 TPS3106 TPS3110 fbd_3106-lvs363.gif

Figure 13. TPS3106 Functional Block Diagram

TPS3103 TPS3106 TPS3110 fbd_3110-lvs363.gif

Figure 14. TPS3110 Functional Block Diagram

8.3 Feature Description

8.3.1 Watchdog

The TPS3110 device integrates a watchdog timer that must be periodically triggered by a positive or negative transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval, RESET becomes active for the time period (t_D). This event also reinitializes the watchdog timer.

8.3.2 Manual Reset (MR)

Many μC-based products require manual-reset capability, allowing an operator or logic circuitry to initiate a reset. Logic low at MR asserts reset. Reset remains asserted while MR is low and for a time period (t_D) after MR returns high. The input has an internal 100-kΩ pullup resistor, so it can be left open if it is unused.

Connect a normally open momentary switch from MR to GND to create a manual reset function. External debounce is not required. If MR is driven from long cables or if the device is used in noisy environments, connecting a 0.1-μF capacitor from MR to GND provides additional noise immunity.

If there is a possibility of transient or DC conditions causing MR to rise above V_DD, a diode should be used to limit MR to a diode drop above V_DD.

8.3.3 PFI, PFO

The TPS3103 has an integrated power-fail (PFI) comparator with a separate open-drain (PFO) output. The PFI and PFO can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply, and has no effect on RESET.

An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail input (PFI) will be compared with an internal voltage reference of 0.551 V. If the input voltage falls below the power-fail threshold (V_{IT – (S)}), the power-fail output (PFO) goes low. If it goes above 0.551 V plus approximately 15-mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise any voltage above 0.551 V. The sum of both resistors should be approximately 1 MΩ, to minimize power consumption and to assure that the current into the PFI pin can be neglected, compared with the current through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail comparator is unused, connect PFI to GND and leave PFO unconnected. For proper operation of the PFI-comparator, the supply voltage (V_DD) must be higher than 0.8 V.

8.3.4 SENSE

The voltage at the SENSE input is compared with a reference voltage of 0.551 V. If the voltage at SENSE falls below the sense-threshold (V_{IT − (S)}), reset is asserted. On the TPS3106 device, a dedicated RSTSENSE output is available. On the TPS3110 device, the logic signal from SENSE is OR-wired with the logic signal from V_DD or MR. An internal timer delays the return of the output to the inactive state, once the voltage at SENSE goes above 0.551 V plus about 15 mV of hysteresis. For proper operation of the SENSE-comparator, the supply voltage must be higher than 0.8 V.

TPS3103 TPS3106 TPS3110 ai_3103_neg_volt-lvs363.gif

1. Resistor may be integrated in microcontroller.

Figure 15. TPS3103 Monitoring a Negative Voltage

TPS3103 TPS3106 TPS3110 ai_3110_dsp-lvs363.gif

Figure 16. TPS3110 in a DSP-System Monitoring Both Supply Voltages

8.4 Device Functional Modes

Table 1. TPS3103 Function Table

MR	V_(PFI) > 0.551 V	V_DD > V_IT–	RESET	PFO
L	0	X⁽¹⁾	L	L
L	1	X	L	H
H	0	0	L	L
H	0	1	H	L
H	1	0	L	H
H	1	1	H	H

(1) X = Don’t care.

Table 2. TPS3106 Function Table

MR	V_(SENSE) > 0.551 V	V_DD > V_IT–	RSTVDD	RSTSENSE
L	X⁽¹⁾	X	L	L
H	0	0	L	L
H	0	1	H	L
H	1	0	L	H
H	1	1	H	H

(1) X = Don’t care.

Table 3. TPS3110 Function Table⁽¹⁾

MR	V_(SENSE) > 0.551 V	V_DD > V_IT–	RESET
L	X⁽²⁾	X	L
H	0	0	L
H	0	1	L
H	1	0	L
H	1	1	H

(1) Function of watchdog timer not shown.

(2) X = Don’t care.